US6124634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Micromachined chip scale package
Assignee: Micron Technology Inc
•
Filing: 1998-09-17
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Granted: 2000-09-26
•
Expires: 2018-09-17
Abstract
Abstract A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
Inventors
- 👤 Salman Akram
- 👤 David R. Hembree
- 👤 Warren M. Farnworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:20
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/01; H10W70/05; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/20; H10W72/221; H10W72/225; H10W72/251; H10W72/252; H10W72/253; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
164 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank made of the same semiconductor material as said at least one semiconductor die is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active side of said at least one semiconductor die and including apertures preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured thereto by said bondable surface with a bonding material to form a laminate comprising said at least one semiconductor die, said passivation layer, and said discrete preformed blank bonded together.
Claim 2
Dependent Claim
164 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank made of the same semiconductor material as said at least one semiconductor die is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active side of said at least one semiconductor die and including apertures preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured thereto by said bondable surface with a bonding material to form a laminate comprising said at least one semiconductor die, said passivation layer, and said discrete preformed blank bonded together.
Claim 3
Dependent Claim
13 words
The package of claim 1, wherein said external electrical connections comprise bond pads.
Claim 4
Dependent Claim
24 words
The package of claim 1, wherein said external electrical connections comprise bond pads and said apertures define elongated grooves extending over said bond pads.
Claim 5
Dependent Claim
17 words
The package of claim 1, wherein said at least one semiconductor die comprises a plurality of dies.
Claim 6
Dependent Claim
13 words
The package according to claim 1 wherein said same semiconductor material comprises silicon.
Claim 7
Dependent Claim
13 words
The package according to claim 1 wherein said same semiconductor material comprises GaAs.
Claim 8
Dependent Claim
15 words
The package according to claim 1 wherein said discrete preformed blank is made from silicon.
Claim 9
Dependent Claim
15 words
The package according to claim 1 wherein said discrete preformed blank is made from GaAs.
Claim 10
Dependent Claim
13 words
The package according to claim 1 wherein said same semiconductor material is ceramic.
Claim 11
Dependent Claim
13 words
The package according to claim 1 wherein said same semiconductor material comprises mullite.
Claim 12
Dependent Claim
18 words
The package of claim 1, wherein at least a portion of the exterior of said laminate is passivated.
Claim 13
Dependent Claim
21 words
The package of claim 2, wherein said apertures are formed through said discrete preformed blank in alignment with said bond pads.
Claim 14
Dependent Claim
188 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die made of a semiconductor material and including an integrated circuit having bond pads on an active side thereof; a passivation layer disposed on said active side of said at least one semiconductor die; a discrete preformed blank made of the same semiconductor material said at least one semiconductor die is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active side of said at least one semiconductor die and including preformed apertures in alignment with said bond pads formed therein through which said bond pads of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured thereto by said bondable surface with a bonding material to form a laminate comprising said at least one semiconductor die, said passivation layer, and said discrete preformed blank bonded together; and wherein said apertures are filled with a conductive material selected from the group comprising: solder, a conductive polymer, and a plated metal.
Claim 15
Dependent Claim
188 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die made of a semiconductor material and including an integrated circuit having bond pads on an active side thereof; a passivation layer disposed on said active side of said at least one semiconductor die; a discrete preformed blank made of the same semiconductor material said at least one semiconductor die is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active side of said at least one semiconductor die and including preformed apertures in alignment with said bond pads formed therein through which said bond pads of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured thereto by said bondable surface with a bonding material to form a laminate comprising said at least one semiconductor die, said passivation layer, and said discrete preformed blank bonded together; and wherein said apertures are filled with a conductive material selected from the group comprising: solder, a conductive polymer, and a plated metal.
Claim 16
Dependent Claim
19 words
The package of claim 13, further including a metal layer over said bond pads and under said conductive material.
Claim 17
Dependent Claim
16 words
The package of claim 14, wherein walls of said apertures are covered with said metal layer.
Claim 18
Dependent Claim
20 words
The chip scale package of claim 13, wherein at least a portion of the exterior of said laminate is passivated.
Claim 19
Dependent Claim
171 words
A chip scale package for a semiconductor die, comprising: a plurality of semiconductor dies made of a semiconductor material and each including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on said active sides of said semiconductor dies; a discrete preformed blank made of the same semiconductor material said plurality of semiconductor dies is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active sides of said plurality of semiconductor dies and including apertures formed therein through which said external electrical connections of said semiconductor dies are accessible, placed over said passivation layer of said active sides of said plurality of semiconductor dies and secured thereto by said bondable surface with a bonding material to form a laminate comprising said plurality of semiconductor dies, said passivation layer, and said discrete preformed blank bonded together; and wherein said plurality of semiconductor dies comprises unsingulated semiconductor dies comprised of at least a portion of a wafer.
Claim 20
Dependent Claim
171 words
A chip scale package for a semiconductor die, comprising: a plurality of semiconductor dies made of a semiconductor material and each including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on said active sides of said semiconductor dies; a discrete preformed blank made of the same semiconductor material said plurality of semiconductor dies is made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active sides of said plurality of semiconductor dies and including apertures formed therein through which said external electrical connections of said semiconductor dies are accessible, placed over said passivation layer of said active sides of said plurality of semiconductor dies and secured thereto by said bondable surface with a bonding material to form a laminate comprising said plurality of semiconductor dies, said passivation layer, and said discrete preformed blank bonded together; and wherein said plurality of semiconductor dies comprises unsingulated semiconductor dies comprised of at least a portion of a wafer.
Claim 21
Dependent Claim
18 words
The package of claim 17, further including a carrier to which said plurality of semiconductor dies is secured.
Claim 22
Dependent Claim
31 words
The package of claim 18, wherein said plurality of semiconductor dies is secured to said carrier in a substantially perpendicular orientation of said active sides to a surface of said carrier.
Claim 23
Dependent Claim
20 words
The chip scale package of claim 17, wherein at least a portion of said exterior of said laminate is passivated.
Claim 24
Dependent Claim
182 words
A chip scale package for a semiconductor die, comprising; a plurality of semiconductor dies made of a semiconductor material and each including an integrated circuit having external electrical connections on an active side thereof: a passivation layer disposed on said active sides of said plurality of semiconductor dies; a discrete preformed blank made of the same semiconductor material said plurality of semiconductor dies are made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active sides of said plurality of semiconductor dies and including apertures preformed therein through which said external electrical connections of said semiconductor dies are accessible, placed over said passivation layer of said active sides of said plurality of semiconductor dies and secured thereto with said bondable surface with a bonding material to form a laminate comprising said plurality of semiconductor dies, said passivation layer, and said discrete preformed blank bonded together; and wherein said plurality of semiconductor dies comprises at least two semiconductor dies secured active side-to-active side with said discrete preformed blank separating said at least two semiconductor dies.
Claim 25
Dependent Claim
182 words
A chip scale package for a semiconductor die, comprising; a plurality of semiconductor dies made of a semiconductor material and each including an integrated circuit having external electrical connections on an active side thereof: a passivation layer disposed on said active sides of said plurality of semiconductor dies; a discrete preformed blank made of the same semiconductor material said plurality of semiconductor dies are made of and having a bondable surface having surface dimensions not in excess of surface dimensions of said active sides of said plurality of semiconductor dies and including apertures preformed therein through which said external electrical connections of said semiconductor dies are accessible, placed over said passivation layer of said active sides of said plurality of semiconductor dies and secured thereto with said bondable surface with a bonding material to form a laminate comprising said plurality of semiconductor dies, said passivation layer, and said discrete preformed blank bonded together; and wherein said plurality of semiconductor dies comprises at least two semiconductor dies secured active side-to-active side with said discrete preformed blank separating said at least two semiconductor dies.
Claim 26
Dependent Claim
20 words
The chip scale package of claim 21, wherein at least a portion of said exterior of said laminate is passivated.
Claim 27
Dependent Claim
131 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank having a bondable surface having dimensions no greater than surface dimensions of said at least one semiconductor die, said discrete preformed blank including apertures defining elongated grooves extending over said external electrical connections preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passication layer of said active sides of said at least one semiconductor die, and secured to said at least one semiconductor die by said bondable surface forming a laminate.
Claim 28
Dependent Claim
131 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank having a bondable surface having dimensions no greater than surface dimensions of said at least one semiconductor die, said discrete preformed blank including apertures defining elongated grooves extending over said external electrical connections preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passication layer of said active sides of said at least one semiconductor die, and secured to said at least one semiconductor die by said bondable surface forming a laminate.
Claim 29
Dependent Claim
147 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die, said at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank made of a material selected from the group comprising silicon, GaAs, ceramic, and mullite, said discrete preformed blank having a bondable surface having dimensions no greater than surface dimensions of said at least one semiconductor die, and said discrete preformed blank including apertures preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured to said at least one semiconductor die by said bondable surface forming a laminate.
Claim 30
Dependent Claim
147 words
A chip scale package for a semiconductor die, comprising: at least one semiconductor die, said at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; a passivation layer disposed on at least said active side of said at least one semiconductor die; and a discrete preformed blank made of a material selected from the group comprising silicon, GaAs, ceramic, and mullite, said discrete preformed blank having a bondable surface having dimensions no greater than surface dimensions of said at least one semiconductor die, and said discrete preformed blank including apertures preformed therein through which said external electrical connections of said at least one semiconductor die are accessible, placed over said passivation layer of said active sides of said at least one semiconductor die and secured to said at least one semiconductor die by said bondable surface forming a laminate.
Claim 31
Dependent Claim
26 words
The chip scale package according to claim 24, wherein said at least one semiconductor die is made of the same material as said discrete preformed blank.
Claim 32
Dependent Claim
41 words
The chip scale package of claim 24, wherein said at least one semiconductor die is a plurality of semiconductor dies and further wherein said plurality of semiconductor dies comprises unsingulated semiconductor dies comprised of at least a portion of a wafer.
Claim 33
Dependent Claim
42 words
The chip scale package of claim 24, wherein said at least one semiconductor die is a plurality of semiconductor dies comprising at least two semiconductor dies secured active side-to-active side with said discrete preformed blank separating said at least two semiconductor dies.
Claim 34
Dependent Claim
70 words
The chip scale package of claim 24, wherein said external electrical connections on said active side of said at least one semiconductor die comprise bond pads, said apertures of said discrete preformed blank are in alignment with said bond pads of said at least one semiconductor die, and said apertures are filled with a conductive material selected from the group comprising a solder, a conductive polymer, and a plated metal.
Claim 35
Dependent Claim
21 words
The chip scale package of claim 28, further comprising a metal layer over said bond pads and under said conductive material.
Claim 36
Dependent Claim
18 words
The chip scale package of claim 28, wherein walls of said apertures are covered with said metal layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-26 | 2004-03-27 | 2004-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-26 | 2008-03-27 | 2008-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-26 | 2012-03-27 | 2012-09-26 | $7700.00 | Window Closed / Lapsed |