Patent US6180469B1 successfully refreshed from Google Patents.
US6180469B1
Expired / Lapsed
US
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Low resistance salicide technology with reduced silicon consumption
Assignee: Advanced Micro Devices Inc
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Filing: 1998-11-06
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Granted: 2001-01-30
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Expires: 2018-11-06
Abstract
Abstract Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.
Inventors
- 👤 Shekhar Pramanick
- 👤 Qi Xiang
- 👤 Ming-Ren Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0215; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10P; H10P14/00; H10P14/40; H10P14/46; H10P32/00; H10P32/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
173 words
A method of manufacturing a semiconductor device, the method comprising sequentially: forming a structure comprising: a silicon-containing substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a silicon-containing gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer formed directly on each side surface of the silicon-containing gate electrode, leaving a portion of each source/drain region exposed; selectively depositing a metal layer on the exposed portions of the source/drain regions and directly on the upper surface of the silicon-containing gate electrode with substantially no metal depositing on the dielectric sidewall spacers; forming a barrier layer within and dividing the metal layer into a lower metal portion below and an upper metal portion above the barrier layer; and heating to react the lower metal portion of each metal layer to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.
Claim 2
Independent Claim
173 words
A method of manufacturing a semiconductor device, the method comprising sequentially: forming a structure comprising: a silicon-containing substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a silicon-containing gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer formed directly on each side surface of the silicon-containing gate electrode, leaving a portion of each source/drain region exposed; selectively depositing a metal layer on the exposed portions of the source/drain regions and directly on the upper surface of the silicon-containing gate electrode with substantially no metal depositing on the dielectric sidewall spacers; forming a barrier layer within and dividing the metal layer into a lower metal portion below and an upper metal portion above the barrier layer; and heating to react the lower metal portion of each metal layer to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.
Claim 3
Dependent Claim
23 words
The method according to claim 1 , wherein the barrier layer prevents reaction of the upper metal portion with underlying silicon during heating.
Claim 4
Dependent Claim
17 words
The method according to claim 1 , comprising ion implanting and annealing to form the barrier layer.
Claim 5
Dependent Claim
23 words
The method according to claim 3 , comprising selectively depositing a metal layer comprising nickel, wherein the metal silicide layer comprises nickel silicide.
Claim 6
Dependent Claim
42 words
The method according to claim 4 , comprising ion implanting nitrogen to form a barrier layer comprising nickel nitride, ion implanting boron to form a barrier layer comprising nickel boride or ion implanting carbon to form a barrier layer comprising nickel carbide.
Claim 7
Dependent Claim
19 words
The method according to claim 5 , comprising ion implanting nitrogen to form a barrier layer comprising nickel nitride.
Claim 8
Dependent Claim
42 words
The method according to claim 6 , comprising ion implanting nitrogen at an implantation dosage of about 1×10 15 atoms cm −2 to about 1×10 17 atoms cm −2 and at an implantation energy of about 10 KeV to about 100 KeV.
Claim 9
Dependent Claim
27 words
The method according to claim 7 , comprising annealing at a temperature of about 200° C. to about 700° C. to form the nickel nitride barrier layer.
Claim 10
Dependent Claim
26 words
The method according to claim 6 , comprising heating at a temperature of about 350° C. to about 750° C. to form the nickel silicide layer.
Claim 11
Dependent Claim
54 words
The method according to claim 1 , wherein; the lower metal portion has a thickness of about 5 Å to about 100 Å; the barrier metal layer has a thickness of about 20 Å to about 300 Å; and the upper metal portion has a thickness of about 500 Å to about 1500 Å.
Claim 12
Dependent Claim
23 words
The method according to claim 3 , comprising simultaneously annealing to form the barrier layer and heating to form the metal silicide layer.
Claim 13
Dependent Claim
31 words
The method according to claim 5 , comprising ion implanting boron to form a barrier layer comprising nickel boride or ion implanting carbon to form a barrier layer comprising nickel carbide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |