US6015752A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Elevated salicide technology
Assignee: GlobalFoundries Inc
•
Filing: 1998-06-30
•
Granted: 2000-01-18
•
Expires: 2018-06-30
Abstract
Abstract Low resistivity metal silicide layers are formed on crystalline source/drain regions and polycrystalline gate electrodes with virtually no consumption of crystalline or polycrystalline silicon, thereby reducing parasitic series resistance without encountering junction leakage. Embodiments include selectively depositing a layer of nickel at a temperature less than about 280° C. on the source/drain region and gate electrode, and then depositing a layer of amorphous silicon at a temperature below about 280° C. thereon. An initial low temperature annealing is conducted, e.g., at about 180° C. to about 280° C., to react the amorphous silicon and nickel to form an upwardly grown layer of amorphous nickel silicide on the source/drain region and gate electrode with virtually no consumption of underlying silicon. Unreacted amorphous silicon is then removed, as by wet etching, and a second high temperature annealing is conducted to convert the high resistivity amorphous nickel silicide to low resistivity polycrystalline nickel silicide.
Inventors
- 👤 Qi Xiang
- 👤 Shekhar Pramanick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
156 words
A method of manufacturing a semiconductor device, the method comprising: forming a structure comprising: a crystalline silicon substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a polycrystalline silicon gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer on each side surface of the gate electrode, leaving a portion of the source/drain regions exposed; selectively depositing a metal layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode with substantially no metal depositing on the dielectric sidewall spacers; depositing a layer of amorphous silicon on the deposited metal layers and sidewall spacers; and heating to react the amorphous silicon with the metal to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.
Claim 2
Independent Claim
156 words
A method of manufacturing a semiconductor device, the method comprising: forming a structure comprising: a crystalline silicon substrate; source/drain regions in the substrate with a channel region therebetween; a gate dielectric layer on the substrate over the channel region; a polycrystalline silicon gate electrode, having an upper surface and side surfaces, on the gate dielectric layer; and a dielectric sidewall spacer on each side surface of the gate electrode, leaving a portion of the source/drain regions exposed; selectively depositing a metal layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode with substantially no metal depositing on the dielectric sidewall spacers; depositing a layer of amorphous silicon on the deposited metal layers and sidewall spacers; and heating to react the amorphous silicon with the metal to form a metal silicide layer on the exposed portions of the source/drain regions and on the upper surface of the gate electrode.
Claim 3
Dependent Claim
12 words
The method according to claim 1, wherein the substrate comprises monocrystalline silicon.
Claim 4
Dependent Claim
26 words
The method according to claim 1, comprising selectively depositing nickel at a temperature less than the temperature at which nickel reacts with crystalline or polycrystalline silicon.
Claim 5
Dependent Claim
18 words
The method according to claim 3, comprising electrolessly depositing nickel at a temperature less than about 280° C.
Claim 6
Dependent Claim
30 words
The method according to claim 3, comprising depositing amorphous silicon at a temperature less than the temperature at which crystalline or polycrystalline silicon reacts with nickel to form nickel silicide.
Claim 7
Dependent Claim
26 words
The method according to claim 5, comprising depositing amorphous silicon by sputtering or low temperature chemical vapor deposition, at a temperature less than about 280° C.
Claim 8
Dependent Claim
53 words
The method according to claim 5, comprising heating to react amorphous silicon with nickel to form a layer of amorphous nickel silicide upwardly on the exposed portions of the source/drain regions and upper surface of the gate electrode, at a temperature below that at which a nickel reacts with crystalline or polycrystalline silicon.
Claim 9
Dependent Claim
63 words
The method according to claim 7, comprising heating to react amorphous silicon with nickel to form the layer of amorphous nickel silicide at a temperature greater than about 180° C. to a temperature less than about 280° C., wherein the layers of amorphous nickel silicide are formed without any substantial consumption of silicon from the substrate or polycrystalline silicon from the gate electrode.
Claim 10
Dependent Claim
13 words
The method according to claim 7, further comprising removing any unreacted amorphous silicon.
Claim 11
Dependent Claim
15 words
The method according to claim 9, comprising removing any unreacted amorphous silicon by wet etching.
Claim 12
Dependent Claim
40 words
The method according to claim 9, further comprising heating at a second temperature, greater than the first temperature, to convert the amorphous nickel silicide into crystalline nickel silicide having a resistivity less than the resistivity of the amorphous nickel silicide.
Claim 13
Dependent Claim
29 words
The method according to claim 11, comprising heating at a temperature of about 450° C. to about 700° C. to convert the amorphous nickel silicide to crystalline nickel silicide.
Claim 14
Dependent Claim
32 words
The method according to claim 1, wherein each source/drain region comprises a shallow extension region under the dielectric sidewall spacer and an adjoining heavily doped drain region exposed on the semiconductor substrate.
Claim 15
Dependent Claim
19 words
The method according to claim 1, wherein the source/drain regions have a junction depth less than about 800 Å.
Claim 16
Dependent Claim
62 words
The method according to claim 11, wherein: the source/drain regions have a junction depth less than about 800 Å; the crystalline nickel silicide layer has a thickness of about 400 Å to about 1000 Å; and the crystalline nickel silicide layer on the source/drain region is spaced apart from the junction depth by a distance no less than the original junction depth.
Claim 17
Dependent Claim
14 words
The method according to claim 1, wherein the gate dielectric layer comprises silicon dioxide.
Claim 18
Dependent Claim
25 words
The method according to claim 1, wherein the dielectric sidewall spacers comprise silicon dioxide, silicon nitride, or a composite of silicon oxide and silicon nitride.
Claim 19
Dependent Claim
143 words
The method according to claim 1, comprising: selectively depositing nickel by electroless plating on the exposed portions of the source/drain regions and on the upper surface of the gate dielectric layer at a temperature less than about 280° C.; depositing the layer of amorphous silicon by low temperature chemical vapor deposition at a temperature less than about 280° C.; heating at a temperature of about 180° C. to less than about 280° C. to react the nickel with the amorphous silicon upwardly, with substantially no consumption of silicon from the substrate or gate electrode, to form a layer of amorphous nickel silicide on the exposed portions of the source/drain regions and the gate electrode; removing unreacted amorphous silicon; and heating to convert the layers of amorphous nickel silicide to crystalline nickel silicide having a lower resistivity than the resistivity of amorphous nickel silicide.
References Cited (Backward Citations)
US4297393A
Cited
US4663820A
Cited
US4692349A
Cited
US4835112A
Cited
US5721175A
Cited
US5608232A
Cited
US5623161A
Cited
US5861340A
Cited
US5780362A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-17 | 2003-07-19 | 2004-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-17 | 2007-07-19 | 2008-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-17 | 2011-07-19 | 2012-01-18 | $7700.00 | Window Closed / Lapsed |