US6037233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metal-encapsulated polysilicon gate and interconnect
Assignee: Bell Semiconductor LLC
•
Filing: 1998-04-27
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Granted: 2000-03-14
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Expires: 2018-04-27
Abstract
Abstract Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
Inventors
- 👤 Yauh-Ching Liu
- 👤 Gary K. Giust
- 👤 Ruggero Castagnetti
- 👤 Subramanian Ramesh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0215; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322; H10D64/60; H10D64/66; H10D64/671; H10D30/0223
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
115 words
A method of fabricating a semiconductor device, comprising: providing a partially-formed electronic device including a semiconductor substrate having a gate dielectric and a gate electrode with horizontal and vertical surfaces formed thereon, and doped source and drain active regions on either side of said gate electrode; selectively depositing a first metal layer on the horizontal and vertical surfaces of said gate electrode; forming spacer dielectric regions disposed between portions of said first metal-layered gate electrode and said doped source and drain active regions, such that said gate electrode is isolated from said source and drain active regions; and selectively depositing a second metal layer on exposed surfaces of said doped source and drain active regions.
Claim 2
Independent Claim
115 words
A method of fabricating a semiconductor device, comprising: providing a partially-formed electronic device including a semiconductor substrate having a gate dielectric and a gate electrode with horizontal and vertical surfaces formed thereon, and doped source and drain active regions on either side of said gate electrode; selectively depositing a first metal layer on the horizontal and vertical surfaces of said gate electrode; forming spacer dielectric regions disposed between portions of said first metal-layered gate electrode and said doped source and drain active regions, such that said gate electrode is isolated from said source and drain active regions; and selectively depositing a second metal layer on exposed surfaces of said doped source and drain active regions.
Claim 3
Dependent Claim
22 words
The method of claim 1, wherein said substrate comprises silicon, said gate dielectric comprises silicon dioxide, and said gate electrode comprises polysilicon.
Claim 4
Dependent Claim
63 words
The method of claim 1, wherein said step of forming spacer dielectric regions comprises: forming a layer of spacer dielectric over said first metal-coated gate electrode, and gate dielectric; and removing spacer dielectric deposited on horizontal surfaces of said first metal-coated gate electrode and gate dielectric, so that vertical dielectric spacers remain on the vertical sidewall surfaces of said first metal-coated gate electrode.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein said first metal layer comprises at least one of tungsten, aluminum, palladium, and nickel.
Claim 6
Dependent Claim
13 words
The method of claim 1, wherein said first metal layer consists of tungsten.
Claim 7
Dependent Claim
15 words
The method of claim 1, wherein said selective deposition is done by chemical vapor deposition.
Claim 8
Dependent Claim
13 words
The method of claim 3, wherein said removal is done by anisotropic etching.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein said second metal layer comprises at least one of tungsten, aluminum, palladium, and nickel.
Claim 10
Dependent Claim
15 words
The method of claim 1, wherein said first and second metal layers comprise different metals.
Claim 11
Dependent Claim
13 words
The method of claim 1, wherein said second metal layer consists of aluminum.
Claim 12
Dependent Claim
17 words
The method of claim 1, wherein said first metal layer is about 200 to 1500 Å thick.
Claim 13
Dependent Claim
19 words
The method of claim 1, wherein said gate electrode has a length of no more than about 0.5 microns.
Claim 14
Dependent Claim
19 words
The method of claim 1, wherein said gate electrode has a length of no more than about 0.25 microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |