US6175129B1
Expired / Lapsed
US
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Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures
Assignee: Micron Technology Inc
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Filing: 1999-03-23
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Granted: 2001-01-16
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Expires: 2019-03-23
Abstract
Abstract Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer. The invention also includes a construction comprising: a) an opening extending through an insulative layer to a node location; b) a conductive spacer within the opening and narrowing at least a portion of the opening; the conductive spacer having inner and outer surfaces; c) a storage node layer in connecting with the node location and extending along both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; and d) a dielectric layer and a cell plate layer operatively proximate the storage node.
Inventors
- 👤 Yauh-Ching Liu
- 👤 David Y. Kao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:50
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/716; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
145 words
A capacitor construction comprising: a node location supported by a substrate; an insulative layer over the node location and over at least a portion of the substrate proximate the node location; a first opening extending through the insulative layer to the node location; a conductive material atop the insulative layer having a second opening therein which joins with the first opening; the conductive material having an inner surface defining a periphery of the second opening and a laterally opposing outer surface; a storage node layer extending along and in electrical connection with the node location and both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer proximate the storage node; and a capacitor cell plate layer separated from the storage node layer by the capacitor dielectric layer.
Claim 2
Dependent Claim
145 words
A capacitor construction comprising: a node location supported by a substrate; an insulative layer over the node location and over at least a portion of the substrate proximate the node location; a first opening extending through the insulative layer to the node location; a conductive material atop the insulative layer having a second opening therein which joins with the first opening; the conductive material having an inner surface defining a periphery of the second opening and a laterally opposing outer surface; a storage node layer extending along and in electrical connection with the node location and both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer proximate the storage node; and a capacitor cell plate layer separated from the storage node layer by the capacitor dielectric layer.
Claim 3
Dependent Claim
15 words
The capacitor construction claim 1 wherein the storage node layer comprises doped hemispherical grain polysilicon.
Claim 4
Dependent Claim
150 words
A capacitor construction comprising: a node location supported by a substrate; an insulative layer over the node location and over at least a portion of the substrate proximate the node location; a first opening extending through the insulative layer to the node location; a conductive material atop the insulative layer proximate the node location and having a second opening therein which joins with and extends the first opening; the conductive material having inner and outer surfaces, the inner surface being a periphery of the second opening; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.
Claim 5
Dependent Claim
150 words
A capacitor construction comprising: a node location supported by a substrate; an insulative layer over the node location and over at least a portion of the substrate proximate the node location; a first opening extending through the insulative layer to the node location; a conductive material atop the insulative layer proximate the node location and having a second opening therein which joins with and extends the first opening; the conductive material having inner and outer surfaces, the inner surface being a periphery of the second opening; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.
Claim 6
Dependent Claim
17 words
The capacitor of claim 3 wherein the conductive material comprises polysilicon doped with a conductivity enhancing dopant.
Claim 7
Dependent Claim
158 words
A capacitor construction comprising: a node location supported by substrate; an insulative layer over the node location and the substrate; a first opening extending through the insulative layer to the node location; a conductive material over the insulative layer and having a lowermost surface which is above the node location; a second opening extending through the conductive material to join with and extend the first opening, the conductive material having inner and outer surfaces, the inner surface being a periphery of the second opening; a storage node layer in electrical contact with the node location and extending along and in substantial contact with both of the inner and outer surfaces of the conductive material, the storage node layer conductive material together forming a capacitor storage node; a capacitor dielectric layer extending along the storage node; and a capacitor cell plate layer extending along the capacitor dielectric layer and separated from the storage node by the capacitor dielectric layer.
Claim 8
Dependent Claim
158 words
A capacitor construction comprising: a node location supported by substrate; an insulative layer over the node location and the substrate; a first opening extending through the insulative layer to the node location; a conductive material over the insulative layer and having a lowermost surface which is above the node location; a second opening extending through the conductive material to join with and extend the first opening, the conductive material having inner and outer surfaces, the inner surface being a periphery of the second opening; a storage node layer in electrical contact with the node location and extending along and in substantial contact with both of the inner and outer surfaces of the conductive material, the storage node layer conductive material together forming a capacitor storage node; a capacitor dielectric layer extending along the storage node; and a capacitor cell plate layer extending along the capacitor dielectric layer and separated from the storage node by the capacitor dielectric layer.
Claim 9
Dependent Claim
24 words
The capacitor of claim 5 wherein the storage node layer extends along an entirety of the inner and outer surfaces of the conductive material.
Claim 10
Dependent Claim
17 words
The capacitor of claim 5 wherein the conductive material comprises polysilicon doped with a conductivity enhancing dopant.
Claim 11
Dependent Claim
25 words
The capacitor of claim 5 wherein the substrate is a semiconductive wafer and wherein the node location comprises a diffusion region within the semiconductive wafer.
Claim 12
Dependent Claim
187 words
A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a first opening extending through the insulative layer to the first diffusion region; a conductive material over the insulative material and having a second opening extending therethrough, the second opening joining with and extending the first opening; the conductive material having inner and outer surfaces, the inner surface forming a periphery of the second opening; a storage node layer in physical contact with the first diffusion region and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; the capacitor dielectric layer, capacitor cell plate layer and storage node together comprising a capacitor; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.
Claim 13
Dependent Claim
187 words
A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a first opening extending through the insulative layer to the first diffusion region; a conductive material over the insulative material and having a second opening extending therethrough, the second opening joining with and extending the first opening; the conductive material having inner and outer surfaces, the inner surface forming a periphery of the second opening; a storage node layer in physical contact with the first diffusion region and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; the capacitor dielectric layer, capacitor cell plate layer and storage node together comprising a capacitor; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.
Claim 14
Dependent Claim
168 words
A monolithic integrated circuit comprising: fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitor constructions and resistive elements; at least one of the capacitor constructions comprising: a node location supported by a substrate; an insulative layer over the substrate; a first contact opening extending through the insulative layer to the node location; a conductive material over the insulative layer and having a second opening extending therethrough, the second opening joining with the first opening; the conductive spacer having an inner surface defining a periphery of the second opening, and having an outer surface laterally opposing the inner surface; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer proximate the storage node; and a capacitor cell plate layer separated from the storage node by the capacitor dielectric layer.
Claim 15
Dependent Claim
168 words
A monolithic integrated circuit comprising: fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitor constructions and resistive elements; at least one of the capacitor constructions comprising: a node location supported by a substrate; an insulative layer over the substrate; a first contact opening extending through the insulative layer to the node location; a conductive material over the insulative layer and having a second opening extending therethrough, the second opening joining with the first opening; the conductive spacer having an inner surface defining a periphery of the second opening, and having an outer surface laterally opposing the inner surface; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive material, the storage node layer and conductive material together forming a capacitor storage node; a capacitor dielectric layer proximate the storage node; and a capacitor cell plate layer separated from the storage node by the capacitor dielectric layer.
Claim 16
Dependent Claim
17 words
The monolithic integrated circuit of claim 10 wherein the integrated circuit is part of a microprocessor circuit.
Claim 17
Dependent Claim
30 words
The monolithic integrated circuit of claim 10 wherein the integrated circuit is part of a microprocessor circuit and wherein the at least one capacitor is incorporated into a DRAM cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-16 | 2004-07-17 | 2005-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-16 | 2008-07-17 | 2009-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-16 | 2012-07-17 | 2013-01-16 | $7700.00 | Window Closed / Lapsed |