Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures

Claim 2

A capacitor comprising: a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.

Claim 3

The capacitor of claim 1 wherein the storage node layer substantially contacts portions of both the inner and outer surfaces of the conductive spacer.

Claim 4

The capacitor of claim 1 wherein the conductive spacer comprises polysilicon doped with a conductivity enhancing dopant.

Claim 5

A capacitor comprising: a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location, the contact opening have an upper portion and a lower portion; a spacer within the upper portion of the contact opening and narrowing the upper portion of the contact opening, the spacer having a bottom surface which is above the node location, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed upper portion of the contact opening; a storage node layer in electrical contact with the node location and extending along and in substantial contact with both of the inner and outer surfaces of the spacer, the storage node layer and spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.

Claim 6

A capacitor comprising: a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location, the contact opening have an upper portion and a lower portion; a spacer within the upper portion of the contact opening and narrowing the upper portion of the contact opening, the spacer having a bottom surface which is above the node location, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed upper portion of the contact opening; a storage node layer in electrical contact with the node location and extending along and in substantial contact with both of the inner and outer surfaces of the spacer, the storage node layer and spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.

Claim 7

The capacitor of claim 4 wherein the storage node layer extends along an entirety of the inner and outer surfaces of the spacer.

Claim 8

The capacitor of claim 4 wherein the spacer comprises polysilicon doped with a conductivity enhancing dopant.

Claim 9

The capacitor of claim 4 wherein the substrate is a semiconductive wafer and wherein the node location comprises a diffusion region within the semiconductive wafer.

Claim 10

A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the first diffusion region; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the first diffusion region and extending along and in electrical connection with both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; the capacitor dielectric layer, capacitor cell plate layer and storage node together comprising a capacitor; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.

Claim 11

A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the first diffusion region; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the first diffusion region and extending along and in electrical connection with both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; the capacitor dielectric layer, capacitor cell plate layer and storage node together comprising a capacitor; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.

Claim 12

A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the first diffusion region, the contact opening have an upper portion and a lower portion; a spacer within the upper portion of the contact opening and narrowing the upper portion of the contact opening, the spacer having a bottom surface which is above the node location, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed upper portion of the contact opening; a storage node layer in electrical contact with the first diffusion region and extending along and in substantial contact with both of the inner and outer surfaces of the spacer; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.

Claim 13

A DRAM cell comprising: a transistor gate over a semiconductor substrate; first and second diffusion regions within the semiconductor wafer substrate operatively proximate the transistor gate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the first diffusion region, the contact opening have an upper portion and a lower portion; a spacer within the upper portion of the contact opening and narrowing the upper portion of the contact opening, the spacer having a bottom surface which is above the node location, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed upper portion of the contact opening; a storage node layer in electrical contact with the first diffusion region and extending along and in substantial contact with both of the inner and outer surfaces of the spacer; a capacitor dielectric layer operatively proximate the storage node; a capacitor cell plate layer operatively proximate the capacitor dielectric layer; and a bitline in electrical connection with the second diffusion region and electrically coupled to the capacitor through the transistor gate.

Claim 14

A monolithic integrated circuit comprising: fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements; at least one of the capacitors comprising: a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.

Claim 15

A monolithic integrated circuit comprising: fabricated circuitry over a semiconductor substrate, the integrated circuitry comprising transistors, capacitors and resistive elements; at least one of the capacitors comprising: a node location within a substrate; an insulative layer over the substrate; a contact opening extending through the insulative layer to the node location; a conductive spacer within the contact opening and narrowing at least a portion of the contact opening; the conductive spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed portion of the contact opening; a storage node layer in physical contact with the node location and extending along and in electrical connection with both of the inner and outer surfaces of the conductive spacer, the storage node layer and conductive spacer together forming a capacitor storage node; a capacitor dielectric layer operatively proximate the storage node; and a capacitor cell plate layer operatively proximate the capacitor dielectric layer.

Claim 16

The monolithic integrated circuit of claim 10 wherein the integrated circuit is part of a microprocessor circuit.

Claim 17

The monolithic integrated circuit of claim 10 wherein the integrated circuit is part of a microprocessor circuit and wherein the at least one capacitor is incorporated into a DRAM cell.