US5283455A
Expired / Lapsed
US
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Thin film field effect element having an LDD structure
Assignee: Mitsubishi Electric Corp
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Filing: 1992-07-10
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Granted: 1994-02-01
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Expires: 2012-07-10
Abstract
Abstract An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.
Inventors
- 👤 Yasuo Inoue
- 👤 Tadashi Nishimura
- 👤 Motoi Ashida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/0312; H10D30/0316; H10D30/0318; H10D30/6717; H10D30/6728
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
99 words
A thin film field effect element, comprising: a gate electrode formed on a surface of an insulating base layer a gate insulating layer formed on said surface of the insulating base layer and surfaces of said gate electrode; a semiconductor layer formed on surfaces of said gate insulating layer; a channel region formed in said semiconductor layer on a side surface of said gate electrode; impurity regions of low concentration formed in said semiconductor layer adjacent to said channel region; and impurity regions of high concentration formed in said semiconductor layer adjacent to said impurity regions of low concentration.
Claim 2
Dependent Claim
99 words
A thin film field effect element, comprising: a gate electrode formed on a surface of an insulating base layer a gate insulating layer formed on said surface of the insulating base layer and surfaces of said gate electrode; a semiconductor layer formed on surfaces of said gate insulating layer; a channel region formed in said semiconductor layer on a side surface of said gate electrode; impurity regions of low concentration formed in said semiconductor layer adjacent to said channel region; and impurity regions of high concentration formed in said semiconductor layer adjacent to said impurity regions of low concentration.
Claim 3
Dependent Claim
40 words
The thin film field effect element according to claims 1, further comprising a sidewall insulating layer adjacent a vertical side surface of said semiconductor layer; one of said impurity regions of low concentration being located under said sidewall insulating layer.
Claim 4
Dependent Claim
30 words
The thin film field effect element according to claim 1, wherein an upper insulating layer is formed between an upper surface of said gate electrode and said gate insulating layer.
Claim 5
Dependent Claim
30 words
The thin film field effect element according to claim 2, wherein an upper insulating layer is formed between an upper surface of said gate electrode and said gate insulating layer.
Claim 6
Dependent Claim
174 words
A thin film field effect element, comprising: a gate electrode formed on an insulating base layer, and having a pair of first and second side surfaces facing to each other and an upper surface; an upper insulating layer formed on said upper surface of the gate electrode; a gate insulating layer formed on surfaces of said gate electrode and said upper insulating layer; a semiconductor layer formed on surfaces of said gate insulating layer and said base layer; first and second channel regions formed in said semiconductor layer facing to said first and said second side surfaces, respectively, of said gate electrode; and first and second source/drain regions formed in portions of said semiconductor layer located on said base layer and a third source/drain region formed in a portion of said semi-conductor layer located on said upper insulating layer; wherein each of said first, second and third source/drain regions includes impurity regions of high concentration and impurity regions of low concentration adjacent to at least one of said first and said second channel region.
Claim 7
Dependent Claim
174 words
A thin film field effect element, comprising: a gate electrode formed on an insulating base layer, and having a pair of first and second side surfaces facing to each other and an upper surface; an upper insulating layer formed on said upper surface of the gate electrode; a gate insulating layer formed on surfaces of said gate electrode and said upper insulating layer; a semiconductor layer formed on surfaces of said gate insulating layer and said base layer; first and second channel regions formed in said semiconductor layer facing to said first and said second side surfaces, respectively, of said gate electrode; and first and second source/drain regions formed in portions of said semiconductor layer located on said base layer and a third source/drain region formed in a portion of said semi-conductor layer located on said upper insulating layer; wherein each of said first, second and third source/drain regions includes impurity regions of high concentration and impurity regions of low concentration adjacent to at least one of said first and said second channel region.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |