Method of forming a capacitor

Claim 1

A method of forming memory cell capacitors over n-channel transistors comprising the following steps: providing an array of word lines atop a semiconductor wafer, and defining first regions adjacent the word lines for formation of first n-channel active areas for electrical connection with memory cell capacitors, and defining second regions adjacent the word lines for formation of second n-channel active areas for electrical connection with bit lines; conducting a p-type LDD halo implant into the second regions for use in formation of LDD regions for the second n-channel active areas; depositing a first layer of insulating material to a selected thickness over the word lines and halo implanted second regions; anisotropically etching the layer of insulating material to define first word line sidewall spacers and to expose the first and second regions; after first spacer formation, conducting an n- LDD implant into the first and second regions; depositing a second layer of insulating material to a selected thickness over the word lines and n- LDD implanted first and second regions; etching the second layer of insulating material to define second word line spacers over the first word line spacers; etching the second layer of material to re-expose the first regions; conducting an n+ implant into the second regions; depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; providing a layer of storage node polysilicon doped with a conductivity enhancing impurity atop the layer of first conductive material, the layer of first conductive material functioning as a diffusion barrier for restricting the conductivity enhancing impurity from migrating downwardly into the wafer; etching the storage node polysilicon layer selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; etching at least some of the exposed first conductive material from underlying substrate; depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; depositing a layer of cell polysilicon atop the capacitor dielectric layer; etching the cell polysilicon selectively relative to the capacitor dielectric layer to define memory cell capacitors which electrically connect with the first active regions; and etching the capacitor dielectric selectively relative to underlying substrate.

Claim 2

A method of forming memory cell capacitors over n-channel transistors comprising the following steps: providing an array of word lines atop a semiconductor wafer, and defining first regions adjacent the word lines for formation of first n-channel active areas for electrical connection with memory cell capacitors, and defining second regions adjacent the word lines for formation of second n-channel active areas for electrical connection with bit lines; conducting a p-type LDD halo implant into the second regions for use in formation of LDD regions for the second n-channel active areas; depositing a first layer of insulating material to a selected thickness over the word lines and halo implanted second regions; anisotropically etching the layer of insulating material to define first word line sidewall spacers and to expose the first and second regions; after first spacer formation, conducting an n- LDD implant into the first and second regions; depositing a second layer of insulating material to a selected thickness over the word lines and n- LDD implanted first and second regions; etching the second layer of insulating material to define second word line spacers over the first word line spacers; etching the second layer of material to re-expose the first regions; conducting an n+ implant into the second regions; depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; providing a layer of storage node polysilicon doped with a conductivity enhancing impurity atop the layer of first conductive material, the layer of first conductive material functioning as a diffusion barrier for restricting the conductivity enhancing impurity from migrating downwardly into the wafer; etching the storage node polysilicon layer selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; etching at least some of the exposed first conductive material from underlying substrate; depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; depositing a layer of cell polysilicon atop the capacitor dielectric layer; etching the cell polysilicon selectively relative to the capacitor dielectric layer to define memory cell capacitors which electrically connect with the first active regions; and etching the capacitor dielectric selectively relative to underlying substrate.

Claim 12

A method of forming memory cell capacitors over n-channel transistors comprising the following steps: a) providing an array of word lines atop a semiconductor wafer, and defining first regions adjacent the word lines for formation of first n-channel active areas for electrical connection with memory cell capacitors, and defining second regions adjacent the word lines for formation of second n-channel active areas for electrical connection with bit lines; b) conducting a p-type LDD halo implant into the second regions for use in formation of LDD regions for the second n-channel active areas; c) depositing a first layer of first insulating material to a selected thickness over the word lines and halo implanted second regions; d) anisotropically etching the layer of insulating material to define first word line sidewall spacers and to expose the first and second regions; e) after first spacer formation, conducting an n- LDD implant into the first and second regions; f) depositing a sacrificial layer of material to a selected thickness over the word lines and n- LDD implanted first and second regions, the sacrificial layer being selectively etchable relative to silicon and the first insulating material; g) anisotropically etching the sacrificial layer to define second sacrificial word line spacers over the first word line spacers; h) conducting an n+ implant into the second regions; i) selectively etching the sacrificial layer from the wafer to re-expose the first regions; j) depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; k) providing a layer of storage node polysilicon doped with a conductivity enhancing impurity atop the layer of first conductive material, the layer of first conductive material functioning as a diffusion barrier for restricting conductivity enhancing impurity from migrating downwardly into the wafer; l) etching the storage node polysilicon selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; m) etching at least some of the exposed first conductive material from underlying substrate; n) depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; o) depositing a layer of cell polysilicon atop the capacitor dielectric layer; p) etching the cell polysilicon selectively relative to the capacitor dielectric layer to define memory cell capacitors which electrically connect with the first active regions; and q) etching the capacitor dielectric selectively relative to underlying substrate.

Claim 13

A method of forming memory cell capacitors over n-channel transistors comprising the following steps: a) providing an array of word lines atop a semiconductor wafer, and defining first regions adjacent the word lines for formation of first n-channel active areas for electrical connection with memory cell capacitors, and defining second regions adjacent the word lines for formation of second n-channel active areas for electrical connection with bit lines; b) conducting a p-type LDD halo implant into the second regions for use in formation of LDD regions for the second n-channel active areas; c) depositing a first layer of first insulating material to a selected thickness over the word lines and halo implanted second regions; d) anisotropically etching the layer of insulating material to define first word line sidewall spacers and to expose the first and second regions; e) after first spacer formation, conducting an n- LDD implant into the first and second regions; f) depositing a sacrificial layer of material to a selected thickness over the word lines and n- LDD implanted first and second regions, the sacrificial layer being selectively etchable relative to silicon and the first insulating material; g) anisotropically etching the sacrificial layer to define second sacrificial word line spacers over the first word line spacers; h) conducting an n+ implant into the second regions; i) selectively etching the sacrificial layer from the wafer to re-expose the first regions; j) depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; k) providing a layer of storage node polysilicon doped with a conductivity enhancing impurity atop the layer of first conductive material, the layer of first conductive material functioning as a diffusion barrier for restricting conductivity enhancing impurity from migrating downwardly into the wafer; l) etching the storage node polysilicon selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; m) etching at least some of the exposed first conductive material from underlying substrate; n) depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; o) depositing a layer of cell polysilicon atop the capacitor dielectric layer; p) etching the cell polysilicon selectively relative to the capacitor dielectric layer to define memory cell capacitors which electrically connect with the first active regions; and q) etching the capacitor dielectric selectively relative to underlying substrate.

Claim 25

A method of forming memory cell capacitors comprising the following steps: providing an array of electrically insulated word lines atop a semiconductor wafer; defining first active regions adjacent the word lines for connection with memory cell capacitors; defining second active regions adjacent the word lines for electrical connection with bit lines; etching to expose the first active regions without use of photomasking; depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first active regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; providing a layer of electrically conductive storage node polysilicon atop the layer of first conductive material; etching the storage node polysilicon layer selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; providing a layer of electrically conductive cell polysilicon atop the capacitor dielectric layer; and selectively at least some of the etching exposed first conductive material from underlying substrate.

Claim 26

A method of forming memory cell capacitors comprising the following steps: providing an array of electrically insulated word lines atop a semiconductor wafer; defining first active regions adjacent the word lines for connection with memory cell capacitors; defining second active regions adjacent the word lines for electrical connection with bit lines; etching to expose the first active regions without use of photomasking; depositing to a selected thickness a layer of first conductive material atop the wafer to conductively connect with the first active regions, the first conductive material being selectively etchable relative to silicon with silicon being selectively etchable relative to the first conductive material; providing a layer of electrically conductive storage node polysilicon atop the layer of first conductive material; etching the storage node polysilicon layer selectively relative to the first conductive material to define isolated capacitor storage nodes and exposed first conductive material; depositing a layer of capacitor dielectric atop the isolated capacitor storage nodes; providing a layer of electrically conductive cell polysilicon atop the capacitor dielectric layer; and selectively at least some of the etching exposed first conductive material from underlying substrate.