US5605857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
Assignee: Micron Technology Inc
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Filing: 1995-02-22
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Granted: 1997-02-25
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Expires: 2015-02-22
Abstract
Abstract A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.
Inventors
- 👤 Mark Jost
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10D1/712; H10D1/714; H10D1/716; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
324 words
A method of forming a bit line over capacitor array of memory cells comprising the following steps: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of electrically insulating material over the word lines and active areas, the layer of insulating material having an uppermost surface which is above the word lines; providing a second contact opening through the insulating material layer to the second active region; providing a first electrically conductive layer over the insulating material upper surface and within the second contact opening which electrically connects with the second active region, the first electrically conductive layer being provided to a thickness which completely fills the second contact opening; providing a first contact opening through the first electrically conductive layer and through the insulating material to the first active region; providing a capacitor storage node electrically conductive layer over the first electrically conductive layer and within the first contact opening which electrically connects with the first active region, the storage node layer being provided to a thickness which less than completely fills the first contact opening; and chemical-mechanical polishing the capacitor storage node layer and the first conductive layer to at least the upper surface of the insulating material, the chemical-mechanical polishing step effectively electrically isolating the first conductive layer material within the second contact opening from the storage node conductive layer material within the first contact opening, the chemical-mechanical polishing step effectively defining a homogeneous second contact plug having a plug upper surface, the chemical-mechanical polishing step effectively defining an isolated capacitor storage node having an upper surface, the upper surfaces of the plug and storage node being elevationally coincident.
Claim 2
Independent Claim
324 words
A method of forming a bit line over capacitor array of memory cells comprising the following steps: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of electrically insulating material over the word lines and active areas, the layer of insulating material having an uppermost surface which is above the word lines; providing a second contact opening through the insulating material layer to the second active region; providing a first electrically conductive layer over the insulating material upper surface and within the second contact opening which electrically connects with the second active region, the first electrically conductive layer being provided to a thickness which completely fills the second contact opening; providing a first contact opening through the first electrically conductive layer and through the insulating material to the first active region; providing a capacitor storage node electrically conductive layer over the first electrically conductive layer and within the first contact opening which electrically connects with the first active region, the storage node layer being provided to a thickness which less than completely fills the first contact opening; and chemical-mechanical polishing the capacitor storage node layer and the first conductive layer to at least the upper surface of the insulating material, the chemical-mechanical polishing step effectively electrically isolating the first conductive layer material within the second contact opening from the storage node conductive layer material within the first contact opening, the chemical-mechanical polishing step effectively defining a homogeneous second contact plug having a plug upper surface, the chemical-mechanical polishing step effectively defining an isolated capacitor storage node having an upper surface, the upper surfaces of the plug and storage node being elevationally coincident.
Claim 3
Dependent Claim
26 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the chemical-mechanical polishing is conducted in a single step.
Claim 4
Dependent Claim
28 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the storage node conductive layer physically contacts the first active region.
Claim 5
Dependent Claim
38 words
The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the storage node conductive layer physically contacts the first active region, and the chemical-mechanical polishing is conducted in a single step.
Claim 6
Dependent Claim
38 words
The method of forming a bit line over capacitor array of memory cells of claim 1 further comprising removing the first conductive layer and the capacitor storage node layer downwardly to below the upper surface of insulating material.
Claim 7
Dependent Claim
48 words
The method of forming a bit line over capacitor array of memory cells of claim 1 further comprising removing the first conductive layer and the capacitor storage node layer downwardly to below the upper surface of insulating material, and the chemical-mechanical polishing is conducted in a single step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |