Circuits and methods for dual-gated transistors

Claim 2

An inverter, comprising: a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the first transistor coupled to the first gate of the first transistor, and wherein the first transistor is a first transistor type and has a threshold voltage level substantially equal to V t1 ; a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the second transistor is a first transistor type and has a threshold voltage level substantially equal to V t2 ; a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the third transistor is a second transistor type and has a threshold voltage level substantially equal to V t2 ; a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the fourth transistor coupled to the first gate of the fourth transistor, and wherein the fourth transistor is a second transistor type and has a threshold voltage level substantially equal to V t1 ; an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter.

Claim 3

The inverter of claim 1, wherein the first and second gates of the first and second transistors are formed of n+ silicon material, and wherein the first and second gates of the third and fourth transistors are formed of p+ silicon material.

Claim 4

The inverter of claim 1, wherein the gate contact interconnects the first gates of the transistors.

Claim 5

The inverter of claim 1, wherein: the first transistor type is an n-channel metal-oxide semiconductor (NMOS) transistor; and the second transistor type is a p-channel metal-oxide semiconductor (PMOS) transistor.

Claim 6

The inverter of claim 1, wherein the first threshold voltage level (V t1 ) of the first and fourth transistors is greater than the second threshold voltage level (V t2 ) of the second and third transistors.

Claim 7

The inverter of claim 1, wherein the transistors are formed on an insulator layer formed on a p- silicon substrate.

Claim 8

The inverter of claim 1, wherein the second gates for the second and third transistors are biased independently from the first gates of the second and third transistors.

Claim 9

A logic circuit, comprising: multiple inverters formed in an array, each inverter comprising: a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the first transistor coupled to the first gate of the first transistor, and wherein the first transistor is a first transistor type and has a threshold voltage level substantially equal to V t1 ; a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the second transistor is a first transistor type and has a threshold voltage level substantially equal to V t2 ; a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the third transistor is a second transistor type and has a threshold voltage level substantially equal to V t2 ; a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the fourth transistor coupled to the first gate of the fourth transistor, and wherein the fourth transistor is a second transistor type and has a threshold voltage level substantially equal to V t1 ; an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter; and a metallization layer that selectively interconnects the inputs and outputs of the inverters to implement a logic function that accepts inputs and produces one or more logical outputs.

Claim 10

A logic circuit, comprising: multiple inverters formed in an array, each inverter comprising: a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the first transistor coupled to the first gate of the first transistor, and wherein the first transistor is a first transistor type and has a threshold voltage level substantially equal to V t1 ; a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the second transistor is a first transistor type and has a threshold voltage level substantially equal to V t2 ; a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the third transistor is a second transistor type and has a threshold voltage level substantially equal to V t2 ; a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the fourth transistor coupled to the first gate of the fourth transistor, and wherein the fourth transistor is a second transistor type and has a threshold voltage level substantially equal to V t1 ; an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter; and a metallization layer that selectively interconnects the inputs and outputs of the inverters to implement a logic function that accepts inputs and produces one or more logical outputs.

Claim 11

The logic circuit of claim 8, wherein the transistors are formed on an insulator layer formed on a p- silicon substrate.

Claim 12

The logic circuit of claim 8, wherein the first and fourth transistors have a higher threshold voltage level than the second and third transistors.

Claim 13

The logic circuit of claim 8, wherein the second gates for the second and third transistors are biased independently from the first gates of the second and third transistors.

Claim 14

The logic circuit of claim 8, wherein the first and second transistors are n-channel metal-oxide semiconductor (NMOS) transistors and the third and fourth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

Claim 15

An input/output device, comprising: a functional circuit having a plurality of components; a logic device coupled to the functional circuit, the logic device having a number of inverters, each inverter comprising: a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the first transistor coupled to the first gate of the first transistor, and wherein the first transistor is a first transistor type and has a threshold voltage level substantially equal to V t1 ; a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the second transistor is a first transistor type and has a threshold voltage level substantially equal to V t2 ; a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the third transistor is a second transistor type and has a threshold voltage level substantially equal to V t2 ; a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the fourth transistor coupled to the first gate of the fourth transistor, and wherein the fourth transistor is a second transistor type and has a threshold voltage level substantially equal to V t1 ; an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter; and a metallization layer that selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.

Claim 16

An input/output device, comprising: a functional circuit having a plurality of components; a logic device coupled to the functional circuit, the logic device having a number of inverters, each inverter comprising: a first transistor extending outwardly from a semiconductor substrate, the first transistor having an upper surface and opposing sidewall surfaces, the first transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the first transistor coupled to the first gate of the first transistor, and wherein the first transistor is a first transistor type and has a threshold voltage level substantially equal to V t1 ; a second transistor extending outwardly from a semiconductor substrate, the second transistor having an upper surface and opposing sidewall surfaces, the second transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the second transistor is a first transistor type and has a threshold voltage level substantially equal to V t2 ; a third transistor extending outwardly from a semiconductor substrate, the third transistor having an upper surface and opposing sidewall surfaces, the third transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, and wherein the third transistor is a second transistor type and has a threshold voltage level substantially equal to V t2 ; a fourth transistor extending outwardly from a semiconductor substrate, the fourth transistor having an upper surface and opposing sidewall surfaces, the fourth transistor having a source/emitter region, a body/base region, a collector/drain region, a first gate on a first one of the opposing sidewall surfaces, and having a second gate on a second one of the opposing sidewall surfaces, the second gate of the fourth transistor coupled to the first gate of the fourth transistor, and wherein the fourth transistor is a second transistor type and has a threshold voltage level substantially equal to V t1 ; an electrical contact between the collector/drain regions of the second and third transistors to provide an output for the inverter; and a gate contact, the gate contact interconnecting the transistors wherein the gate contact provides an input to the inverter; and a metallization layer that selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.

Claim 17

The input/output device of claim 13, wherein the first and fourth transistors have a higher threshold voltage level than the second and third transistors.

Claim 18

The input/output device of claim 13, wherein the second gates for the second and third transistors are biased independently from the first gates of the second and third transistors.

Claim 19

The input/output device of claim 13, wherein the gate contact interconnects the first gates of the transistors.

Claim 20

An inverter circuit, comprising: a complementary pair of transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a source/emitter region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a first gate formed on a first one of the opposing sidewalls; and a second gate formed on a second one of the opposing sidewalls, and wherein the first and second gates in each transistor are coupled to one another; an electrical contact between collector/drain regions of the complementary pair to provide an output for the inverter; and a gate contact, the gate contact interconnecting the first gates of the complementary pair and wherein the gate contact comprises an input to the inverter.

Claim 21

An inverter circuit, comprising: a complementary pair of transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a source/emitter region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a first gate formed on a first one of the opposing sidewalls; and a second gate formed on a second one of the opposing sidewalls, and wherein the first and second gates in each transistor are coupled to one another; an electrical contact between collector/drain regions of the complementary pair to provide an output for the inverter; and a gate contact, the gate contact interconnecting the first gates of the complementary pair and wherein the gate contact comprises an input to the inverter.

Claim 22

The inverter circuit of claim 17, wherein the first channel type transistor comprises an n-channel metal-oxide semiconductor (NMOS) transistor, and wherein the second channel type transistor comprises a p-channel metal-oxide semiconductor (PMOS) transistor.

Claim 23

The inverter circuit of claim 17, further comprising an insulator layer formed between the body region and the substrate.

Claim 24

An information handling system comprising: a central processing unit; a random access memory; and a system bus for communicatively coupling the central processing unit and the random access memory, the central processing unit (CPU) further including an inverter, the inverter further comprising: a complementary pair of transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a source/emitter region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a first gate formed on a first one of the opposing sidewalls; and a second gate formed on a second one of the opposing sidewalls and wherein the first and second gates in each transistor are coupled to one another; an electrical contact between collector/drain regions of the complementary pair to provide an output for the inverter; and a gate contact, the gate contact interconnecting the first gates of the complementary pair wherein the gate contact comprises an input to the inverter.

Claim 25

An information handling system comprising: a central processing unit; a random access memory; and a system bus for communicatively coupling the central processing unit and the random access memory, the central processing unit (CPU) further including an inverter, the inverter further comprising: a complementary pair of transistors, the complementary pair comprising a first channel type transistor and a second channel type transistor, each transistor comprising: a body region formed of single crystalline semiconductor material and extending outwardly from a substrate, the body region having an upper surface and opposing sidewalls; a source/emitter region formed within a portion of the upper surface of the body region; a collector/drain region formed within a portion of the upper surface of the body region; a first gate formed on a first one of the opposing sidewalls; and a second gate formed on a second one of the opposing sidewalls and wherein the first and second gates in each transistor are coupled to one another; an electrical contact between collector/drain regions of the complementary pair to provide an output for the inverter; and a gate contact, the gate contact interconnecting the first gates of the complementary pair wherein the gate contact comprises an input to the inverter.

Claim 26

The information handling system of claim 20, wherein the first channel type transistor comprises an n-channel metal-oxide semiconductor (NMOS) transistor, and wherein the second channel type transistor comprises a p-channel metal-oxide semiconductor (PMOS) transistor.

Claim 27

The information handling system of claim 20, each transistor further comprising an insulator layer formed between the body region and the substrate.