US5250450A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
Assignee: Micron Technology Inc
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Filing: 1992-02-12
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Granted: 1993-10-05
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Expires: 2012-02-12
Abstract
Abstract An insulated-gate vertical FET has a channel region and gate structure that is formed along the sidewall of trench in a P-type semiconductor substrate. The drain and source regions of the FET are formed in the mesa and the base portions of the trench. All contacts to the gate, drain, and source regions can be made from the top surface of the semiconductor substrate. One or more sidewalls of the trench are oxidized with a thin gate oxide dielectric layer followed by a thin polysilicon deposited film to form an insulated gate layer. A reactive ion etch step removes the insulated gate layer from the mesa and the base portions of the trench. An enhanced N-type implant creates the drain and source regions in the mesa and the base portions of the trench. The trench is partially filled with a spacer oxide layer to reduce gate-to-source overlap capacitance. A conformal conductive polysilicon layer is deposited over the insulated gate layer. A portion of the conductive polysilicon layer is extended above the surface of the trench onto the mesa to form a gate contact. A field oxide covers the entire surface of the FET, which is opened in the mesa to form gate and drain contacts, and in the base to form the source contact.
Inventors
- 👤 Ruojia Lee
- 👤 Fernando Gonzalez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:08
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/025; H10D30/60; H10D30/63
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
212 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first conductivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) partially filling the trench with a spacer dielectric layer, by: depositing a spacer dielectric layer atop the surface of the trench; planarizing the spacer dielectric layer on the mesa of the trench; and etching the spacer dielectric layer in the base of the trench to a predetermined thickness; f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface; and g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type.
Claim 2
Independent Claim
212 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first conductivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) partially filling the trench with a spacer dielectric layer, by: depositing a spacer dielectric layer atop the surface of the trench; planarizing the spacer dielectric layer on the mesa of the trench; and etching the spacer dielectric layer in the base of the trench to a predetermined thickness; f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface; and g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type.
Claim 3
Dependent Claim
27 words
A method according to claim 1 including the step of sizing the thickness of the spacer dielectric layer to decrease the parasitic capacitance below a predetermined capacitance.
Claim 4
Dependent Claim
27 words
A method according to claim 2 in which the step of sizing the thickness of the spacer dielectric comprises etching the spacer dielectric to a predetermined thickness.
Claim 5
Dependent Claim
65 words
A method according to claim 1 in which the step of forming an insulated gate layer on the sidewall comprises the steps of: forming a gate dielectric layer on the surface of the trench; forming a gate conductive layer atop the gate dielectric layer; and selectively removing the gate dielectric layer and the gate conductive layer from the mesa and the base of the trench.
Claim 6
Dependent Claim
40 words
A method according to claim 1 in which the step of forming the first layer of the second conductivity type in the mesa comprises forming the first layer of the second conductivity type in a first portion of the mesa.
Claim 7
Dependent Claim
49 words
A method according to claim 5 comprising the steps of: extending the insulated gate layer above the reference surface and onto a second portion of the mesa; and extending the conductive layer above the reference surface and onto the insulated gate layer on the second portion of the mesa.
Claim 8
Dependent Claim
56 words
A method according to claim 6 comprising the steps of: forming a field dielectric layer covering the conductive layer on the second portion of the mesa; opening the field dielectric layer covering the conductive layer on the second portion of the mesa to form a gate contact; and covering the gate contact with an interconnect line.
Claim 9
Dependent Claim
69 words
A method according to claim 5 comprising the steps of: forming a field dielectric layer covering first layer of the second conductivity type on the first portion of the mesa; opening the field dielectric layer above the first layer of the second conductivity type on the first portion of the mesa to form a first current node contact; and covering the first current node contact with an interconnect line.
Claim 10
Independent Claim
164 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first conductivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) forming a conductor that extends from the mesa of the trench to the base of the trench to ohmically contact the second layer of the second conductivity type; f) partially filling the trench with a spacer dielectric layer; and g) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench for ohmic contact with the conductor.
Claim 11
Independent Claim
164 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first conductivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) forming a conductor that extends from the mesa of the trench to the base of the trench to ohmically contact the second layer of the second conductivity type; f) partially filling the trench with a spacer dielectric layer; and g) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench for ohmic contact with the conductor.
Claim 12
Dependent Claim
37 words
A method according to claim 9 in which the step of forming a conductor comprises forming a conductor that is electrically insulated from the insulated gate layer and from the first layer of the second conductivity type.
Claim 13
Dependent Claim
64 words
A method according to claim 9 in which the step of forming an insulated gate layer on the sidewall comprises the steps of: forming a gate dielectric layer on the surface of the trench; forming a gate conductive layer atop the gate dielectric layer; and selectively removing the gate dielectric layer and the conductive layer from the mesa and the base of the trench.
Claim 14
Dependent Claim
57 words
A method according to claim 9 in which the step of partially filling the trench comprises the steps of: depositing a spacer dielectric layer atop the surface of the trench; planarizing the spacer dielectric layer on the mesa of the trench; and etching the spacer dielectric layer in the base of the trench to a predetermined thickness.
Claim 15
Dependent Claim
35 words
A method according to claim 9 including the step of forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer oxide layer to the reference surface.
Claim 16
Dependent Claim
81 words
A method according to claim 9 comprising the steps of: opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench; forming a field dielectric layer covering the second layer the second conductivity type in the base of the trench; opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact; and ohmically contacting the second current node contact with the conductor.
Claim 17
Dependent Claim
40 words
A method according to claim 9 in which the step of forming the first layer of the second conductivity type in the mesa comprises forming the first layer of the second conductivity type in a first portion of the mesa.
Claim 18
Dependent Claim
49 words
A method according to claim 15 comprising the steps of: extending the insulated gate layer above the reference surface and onto a second portion of the mesa; and extending the conductive layer above the reference surface and onto the insulated gate layer on the second portion of the mesa.
Claim 19
Dependent Claim
56 words
A method according to claim 16 comprising the steps of: forming a field dielectric layer covering the conductive layer on the second portion of the mesa; opening the field dielectric layer above the conductive layer on the second portion of the mesa to form a gate contact; and covering the gate contact with an interconnect line.
Claim 20
Dependent Claim
70 words
A method according to claim 15 comprising the steps of: forming a field dielectric layer covering the first layer of the second conductivity type on the first portion of the mesa; opening the field dielectric layer above the first layer of the second conductivity type on the first portion of the mesa to form a first current mode contact; and covering the first current node contact with an interconnect line.
Claim 21
Independent Claim
249 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first condustivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) partially filling the trench with a spacer dielectric layer; f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface; g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type; h) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench; and i) forming a field dielectric layer covering the second layer of the second conductivity type in the base of the trench; j) opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact; and k) covering the second current node contact with an interconnect line.
Claim 22
Independent Claim
249 words
A method of fabricating an insulated-gate vertical field-effect transistor comprising the steps of: a) providing a semiconductor substrate of a first condustivity type having a reference surface; b) forming a trench in the semiconductor substrate, the trench defining a surface including a mesa at the level of the reference surface, a sidewall, and a base recessed from the reference surface; c) forming an insulated gate layer on the sidewall; d) forming a first layer of a second conductivity type in the mesa and a second layer of the second conductivity type in the base of the trench; e) partially filling the trench with a spacer dielectric layer; f) forming a conductive layer along the sidewall of the trench over the insulated gate layer extending from the spacer dielectric layer to the reference surface; g) the conductive layer being spaced apart from the second layer of the second conductivity type by the spacer dielectric layer to decrease a parasitic capacitance between the conductive layer and the second layer of the second conductivity type; h) opening the spacer dielectric layer to expose the layer of the second conductivity type at the base of the trench; and i) forming a field dielectric layer covering the second layer of the second conductivity type in the base of the trench; j) opening the field dielectric layer above the second layer of the second conductivity type to form a second current node contact; and k) covering the second current node contact with an interconnect line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-04 | 1997-04-05 | 1997-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-04 | 2001-04-05 | 2001-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-04 | 2005-04-05 | 2005-10-05 | $7700.00 | Window Closed / Lapsed |