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US4464212A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making high sheet resistivity resistors

Assignee: International Business Machines Corp
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Filing: 1982-12-13
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Granted: 1984-08-07
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Expires: 2002-12-13
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Abstract

Abstract A high sheet resistivity, doped semiconductor resistor is made by a process which produces a resistor diffusion or ion implantation mask having a narrow dimension determined by a "sidewall" technique. The sidewall technique defines the narrow dimension by the thickness of a doped or undoped layer deposited on a different underlying layer having horizontal and vertical surfaces. The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion. The vertical portion, if undoped, is removed to define a diffused or ion-implanted resistor. The vertical portion, if doped, optionally may be removed, after heating to form a diffused resistor, or may be left in place to form a resistor in shunt with the diffused resistor.

Inventors

  • 👤 Harsaran S. Bhatia
  • 👤 Jacob Riseman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 08:38
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40; H10P76/408; H10P76/4085

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 156 words
The method of fabricating a first doped polycrystalline silicon resistor comprising: providing a monocrystalline silicon semiconductor body; forming a first insulator material layer upon a major surface of said body; anisotropically etching said first layer, leaving a substantially vertical edge of said first layer where said resistor is to be formed; forming a second layer of doped polycrystalline silicon material, having a different anisotropic etching characteristic as compared to said first layer, over said first layer; anisotropically etching said second layer to substantially remove the horizontal portions of said second layer and leave the substantially vertical portion of said second layer on said edge of said first layer, thereby forming the body of said first resistor; forming a third layer of said first insulator material over the resulting structure, said third layer being substantially coplanar with said vertical portion of said second layer; and making electrical contact to the terminal portions of said first resistor body.
Claim 2
Independent Claim 156 words
The method of fabricating a first doped polycrystalline silicon resistor comprising: providing a monocrystalline silicon semiconductor body; forming a first insulator material layer upon a major surface of said body; anisotropically etching said first layer, leaving a substantially vertical edge of said first layer where said resistor is to be formed; forming a second layer of doped polycrystalline silicon material, having a different anisotropic etching characteristic as compared to said first layer, over said first layer; anisotropically etching said second layer to substantially remove the horizontal portions of said second layer and leave the substantially vertical portion of said second layer on said edge of said first layer, thereby forming the body of said first resistor; forming a third layer of said first insulator material over the resulting structure, said third layer being substantially coplanar with said vertical portion of said second layer; and making electrical contact to the terminal portions of said first resistor body.
Claim 3
Dependent Claim 62 words
The method of claim 1 wherein said monocrystalline semiconductor body is of a first conductivity type and said doped polycrystalline silicon material is of the opposite conductivity type, and further including: heating said resulting structure so as to diffuse the dopant from said resistor body into said semiconductor body to form a second resistor body in shunt with said first resistor body.

References Cited (Backward Citations)

US4332070A Cited
US4209350A Cited
US4209349A Cited
US4234362A Cited
US4298401A Cited
US4333227A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-08-07 1988-02-06 1988-08-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-08-07 1992-02-06 1992-08-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-08-07 1996-02-06 1996-08-07 $7700.00 Window Closed / Lapsed

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