Method for manufacturing a vertical, grooved MOSFET

Claim 1

A method for fabricating a VMOS device having minimized parasitic bipolar effects, comprising: providing a semiconductor substrate having first and second opposing major surfaces including therein: a substantially planar first conductivity type drain region at the second surface; a substantially planar first conductivity type extended drain region of lower conductivity than the drain region disposed across the drain region; and a second conductivity type body region adjacent to the extended drain region; forming a first conductivity type source region extending from the first surface within the boundaries of the body region; forming a two layer structure over the source region, said structure comprising a secondary mask layer over a primary mask layer; forming a pair of relatively high conductivity body regions, of lower conductivity than the source region, in those areas not covered with the two layer structure, said relatively high conductivity body regions extending from the first surface to approximately the same depth as the lower conductivity body region and diffusing laterally beneath the two layer structure a predetermined distance; undercutting the secondary mask layer a distance greater than said lateral diffusion distance so as to yield the secondary mask layer overhanging the primary mask layer; stripping the secondary mask layer; forming a third mask layer in areas not covered by the primary mask layer; stripping the primary mask layer; forming a groove in the area not masked by the third mask layer, so as to expose the relatively low conductivity body; and forming a gate oxide on the exposed body region in the groove, a gate electrode on the gate oxide, a drain electrode on the drain region at the second surface, and a source electrode on the source region and relatively high conductivity body regions at the first surface.

Claim 2

A method for fabricating a VMOS device having minimized parasitic bipolar effects, comprising: providing a semiconductor substrate having first and second opposing major surfaces including therein: a substantially planar first conductivity type drain region at the second surface; a substantially planar first conductivity type extended drain region of lower conductivity than the drain region disposed across the drain region; and a second conductivity type body region adjacent to the extended drain region; forming a first conductivity type source region extending from the first surface within the boundaries of the body region; forming a two layer structure over the source region, said structure comprising a secondary mask layer over a primary mask layer; forming a pair of relatively high conductivity body regions, of lower conductivity than the source region, in those areas not covered with the two layer structure, said relatively high conductivity body regions extending from the first surface to approximately the same depth as the lower conductivity body region and diffusing laterally beneath the two layer structure a predetermined distance; undercutting the secondary mask layer a distance greater than said lateral diffusion distance so as to yield the secondary mask layer overhanging the primary mask layer; stripping the secondary mask layer; forming a third mask layer in areas not covered by the primary mask layer; stripping the primary mask layer; forming a groove in the area not masked by the third mask layer, so as to expose the relatively low conductivity body; and forming a gate oxide on the exposed body region in the groove, a gate electrode on the gate oxide, a drain electrode on the drain region at the second surface, and a source electrode on the source region and relatively high conductivity body regions at the first surface.

Claim 6

The method of claims 1 or 4 wherein: the primary mask layer is Si 3 N 4 ; and the secondary mask layer is SiO 2 .

Claim 7

The method of claims 1 or 4 wherein: the primary mask layer is Si 3 N 4 ; the secondary mask layer is photoresist; and the undercutting of the photoresist is performed by plasma etching.

Claim 10

The method of claims 7 or 8 wherein: the fourth mask layer is Si 3 N 4 ; the primary mask layer is SiO 2 ; and the secondary mask layer is Si 3 N 4 .

Claim 11

The method of claims 7 or 8 wherein: the fourth mask layer is Si 3 N 4 ; the primary mask layer is SiO 2 ; and the secondary mask layer is photoresist.

Claim 12

The method of claims 4, 7 or 8 wherein: the distance of undercutting is substantially equal to the lateral diffusion distance of the relatively high conductivity body regions.