US4244752A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single mask method of fabricating complementary integrated circuits
Assignee: Samsung Electronics Co Ltd
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Filing: 1979-03-06
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Granted: 1981-01-13
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Expires: 1999-03-06
Abstract
Abstract A method of fabricating an integrated circuit having a plurality of different devices, which method employs a single mask to define the active areas of all such devices. A silicon oxide-silicon nitride layer is formed on the surface of a silicon wafer so as to define the location of subsequent oxide insulating layers which in turn actually define all the active areas of the circuit. Respective active areas for the different devices can then be formed by selective ion implantation.
Inventors
- 👤 Donald L. Henderson, Sr.
- 👤 Steven M. Baldwin
- 👤 Raymond Pong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10P76/00; H10P76/40; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
130 words
A method of fabricating an integrated circuit having both P-channel and N-channel transistors including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of a P-type substrate; patterning said first layer to cover only those areas of said surface that are to be occupied by said P-channel and N-channel transistors; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said P-channel transistors; and doping the substrate surface within the holes of said second layer with N-type atoms to form wells for said P-channel transistors.
Claim 2
Independent Claim
130 words
A method of fabricating an integrated circuit having both P-channel and N-channel transistors including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of a P-type substrate; patterning said first layer to cover only those areas of said surface that are to be occupied by said P-channel and N-channel transistors; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said P-channel transistors; and doping the substrate surface within the holes of said second layer with N-type atoms to form wells for said P-channel transistors.
Claim 3
Dependent Claim
32 words
A method according to claim 1 and further including the step of forming an insulating layer on the portion of said substrate surface that is not covered by said patterned first layer.
Claim 4
Dependent Claim
47 words
A method according to claim 1 wherein said doping step includes the substeps of: implanting said N-type atoms through that portion of said patterned first layer that lies within the holes of said second layer; and heating said substrate to diffuse said implanted atoms into said substrate.
Claim 5
Dependent Claim
22 words
A method according to claim 1 wherein said first layer of material which is impervious to oxygen diffusion consists of silicon nitride.
Claim 6
Independent Claim
130 words
A method of fabricating an integrated circuit having both P-channel and N-channel transistors including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of an N-type substrate; patterning said first layer to cover only those areas of said surface that are to be occupied by said P-channel and N-channel transistors; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said N-channel transistors; and doping the substrate surface within the holes of said second layer with P-type atoms to form wells for said N-channel transistors.
Claim 7
Independent Claim
130 words
A method of fabricating an integrated circuit having both P-channel and N-channel transistors including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of an N-type substrate; patterning said first layer to cover only those areas of said surface that are to be occupied by said P-channel and N-channel transistors; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said N-channel transistors; and doping the substrate surface within the holes of said second layer with P-type atoms to form wells for said N-channel transistors.
Claim 8
Dependent Claim
32 words
A method according to claim 5 and further including the step of forming an insulating layer on the portion of said substrate surface that is not covered by said patterned first layer.
Claim 9
Dependent Claim
47 words
A method according to claim 5 wherein said doping step includes the substeps of: implanting said P-type atoms through that portion of said patterned first layer that lies within the holes of said second layer; and heating said substrate to diffuse said implanted atoms into said substrate.
Claim 10
Dependent Claim
22 words
A method according to claim 5 wherein said first layer of material which is impervious to oxygen diffusion consists of silicon nitride.
Claim 11
Independent Claim
172 words
A method of fabricating an integrated circuit having active devices with majority charge carriers of one conductivity type, and also having active devices with majority charge carriers opposite to said one conductivity type; said method including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of a substrate with dopant atoms of said one conductivity type; patterning said first layer to cover those areas of said surface that are to be occupied by all of said active devices; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said active devices of said one conductivity type; and doping the substrate surface within the holes of said second layer with atoms of said opposite conductivity type to form wells for said active devices of said one conductivity type.
Claim 12
Independent Claim
172 words
A method of fabricating an integrated circuit having active devices with majority charge carriers of one conductivity type, and also having active devices with majority charge carriers opposite to said one conductivity type; said method including the steps of: forming a first layer of material which is impervious to oxygen diffusion therethrough over a major surface of a substrate with dopant atoms of said one conductivity type; patterning said first layer to cover those areas of said surface that are to be occupied by all of said active devices; forming a second layer of photoresist over said substrate surface and patterned first layer; opening holes in said second layer whose perimeters lie between said patterned first layer and expose those portions of said patterned first layer which overly areas to be occupied by said active devices of said one conductivity type; and doping the substrate surface within the holes of said second layer with atoms of said opposite conductivity type to form wells for said active devices of said one conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |