US3928081A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor devices using composite mask and ion implantation
Assignee: Signetics Corp
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Filing: 1973-10-26
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Granted: 1975-12-23
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Expires: 1993-10-26
Abstract
Abstract A method for fabricating semiconductor devices from a semiconductor body having a planar surface by forming on the surface a layer of protective material which is to be utilized as a mask. A plurality of windows are formed simultaneously in the layer of protective material to expose said surface to permit the subsequent formation of isolation regions, base regions and collector contact regions in the semiconductor body. Ion implantation is carried out at low temperatures through certain of the openings while covering the other openings to form the respective regions thereby eliminating the necessity for mask to mask tolerance requirements and tolerances required for thermal diffusions.
Inventors
- 👤 Jr James A Marley
- 👤 Bohumil Polata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:11
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/22; H10P76/00; H10P76/40; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/085
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
315 words
In a method for fabricating semiconductor devices from a semiconductor body having a planar surface, forming a layer of material to be utilized as a mask on said surface, forming substantially simultaneously a plurality of openings in said layer of material exposing said surface, said openings being sized and positioned so that they can be utilized for the formation of a diffusion isolation region, a base region and a collector contact region in the semiconductor body, covering said openings for the formation of the base region and the collector contact region with a material which will prevent impurities from entering said openings for the formation of the base region and the collector contact region, causing impurities to enter the semiconductor body through the opening for the diffusion isolation region so that the impurities will be driven to a substantial depth within the semiconductor body, removing the material covering at least said collector contact region, covering the openings for the diffusion isolation region and the base region, causing impurities to enter the open window for the collector contact region and to penetrate into the semiconductor body to form a collector contact region, removing the material covering at least the opening for said base region, covering at least said opening for the collector contact region with a material through which impurities cannot make a significant penetration, causing an impurity to enter the opening for the base region to define a base region in the semiconductor body, causing an impurity to pass through the opening for the base region to cause the formation of an emitter region within the base region, forming openings in said layer of insulating material exposing portions of said surface overlying the base and emitter regions and the collector contact region And forming a metallic contact extending through said opening and making contact to said base and emitter regions and said collector contact region.
Claim 2
Dependent Claim
315 words
In a method for fabricating semiconductor devices from a semiconductor body having a planar surface, forming a layer of material to be utilized as a mask on said surface, forming substantially simultaneously a plurality of openings in said layer of material exposing said surface, said openings being sized and positioned so that they can be utilized for the formation of a diffusion isolation region, a base region and a collector contact region in the semiconductor body, covering said openings for the formation of the base region and the collector contact region with a material which will prevent impurities from entering said openings for the formation of the base region and the collector contact region, causing impurities to enter the semiconductor body through the opening for the diffusion isolation region so that the impurities will be driven to a substantial depth within the semiconductor body, removing the material covering at least said collector contact region, covering the openings for the diffusion isolation region and the base region, causing impurities to enter the open window for the collector contact region and to penetrate into the semiconductor body to form a collector contact region, removing the material covering at least the opening for said base region, covering at least said opening for the collector contact region with a material through which impurities cannot make a significant penetration, causing an impurity to enter the opening for the base region to define a base region in the semiconductor body, causing an impurity to pass through the opening for the base region to cause the formation of an emitter region within the base region, forming openings in said layer of insulating material exposing portions of said surface overlying the base and emitter regions and the collector contact region And forming a metallic contact extending through said opening and making contact to said base and emitter regions and said collector contact region.
Claim 3
Dependent Claim
39 words
A method as in claim 1 wherein said diffusion isolation region is formed by using ion implantation to implant the impurity and then driving the impurity to a greater depth in the semiconductor body by the use of heat.
Claim 4
Dependent Claim
44 words
A method as in claim 1 wherein said base region is formed by implanting impurities into the base region by the use of ion implantation and wherein the impurities are driven to a greater depth in the base region by the application of heat.
Claim 5
Dependent Claim
25 words
A method as in claim 1 wherein said impurity in the collector contact region is introduced by ion implantation and a subsequent application of heat.
Claim 6
Dependent Claim
18 words
A method as in claim 4 wherein said impurity for the emitter region is introduced by ion implantation.
Claim 7
Dependent Claim
28 words
A method as in claim 3 wherein additional impurities are introduced into the isolation diffusion region during the time the impurities are being introduced into the base region.
Claim 8
Dependent Claim
36 words
A method as in claim 1 wherein the semiconductor body includes an epitaxial layer and wherein said isolation diffusion region, said base and emitter regions and said collector contact region are disposed in the epitaxial layer.
Claim 9
Dependent Claim
23 words
A method as in claim 7 together with the step of forming a buried layer in the semiconductor body below the epitaxial layer.
Claim 10
Dependent Claim
32 words
A method as in claim 1 wherein said layer of material on said surface to be utilized as a mask is silicon dioxide and wherein said semiconductor body is formed with silicon.
Claim 11
Independent Claim
78 words
A METHOD FOR FABRICATING SEMICONDUCTOR DEVICES FROM A SEMICONDUCTOR BODY HAVING A PLANAR SURFACE, FORMING A LAYER OF MATERIAL TO BE UTILIZED AS A MASK ON SAID SURFACE, FORMING SUBSTANTIALLY SIMULTANEOUSLY A PLURALITY OF OPENINGS IN THE LAYER OF MATERIAL TO EXPOSE AREAS OF SAID SURFACE, SELECTIVELY DOPING THE EXPOSED AREAS DEFINED BY SAID OPENINGS IN SEQUENCE AND SELECTIVELY COVERING SAID OPENINGS SO THAT THE AREAS EXPOSED THEREBY ARE NOT DOPED UNTIL THE PROPER TIME IN SAID SEQUENCE.
Claim 12
Independent Claim
78 words
A METHOD FOR FABRICATING SEMICONDUCTOR DEVICES FROM A SEMICONDUCTOR BODY HAVING A PLANAR SURFACE, FORMING A LAYER OF MATERIAL TO BE UTILIZED AS A MASK ON SAID SURFACE, FORMING SUBSTANTIALLY SIMULTANEOUSLY A PLURALITY OF OPENINGS IN THE LAYER OF MATERIAL TO EXPOSE AREAS OF SAID SURFACE, SELECTIVELY DOPING THE EXPOSED AREAS DEFINED BY SAID OPENINGS IN SEQUENCE AND SELECTIVELY COVERING SAID OPENINGS SO THAT THE AREAS EXPOSED THEREBY ARE NOT DOPED UNTIL THE PROPER TIME IN SAID SEQUENCE.
Claim 13
Dependent Claim
21 words
A method as in claim 10 wherein a material which can be readily removed is utilized for selectively covering said openings.
Claim 14
Dependent Claim
12 words
A method as in claim 11 wherein said material is a photoresist.
Claim 15
Dependent Claim
12 words
A method as in claim 11 wherein said material is a metal.
Claim 16
Dependent Claim
30 words
A method as in claim 11 wherein said material covering said openings is selectively removed and subjecting the semiconductor body to heat to cause thermal diffusion of the doped impurities.
Claim 17
Dependent Claim
17 words
A method as in claim 10 wherein said areas are doped by the use of ion implantation.
Claim 18
Dependent Claim
35 words
A method as in claim 10 wherein said areas are doped by first implanting impurities by use of ion implantation and subsequently driving them to a greater depth in the semiconductor body by thermal diffusion.
Claim 19
Dependent Claim
31 words
A method as in claim 11 wherein said openings can be selectively covered by forming said material over said openings so that they substantially overlap said openings in non-critical alignment steps.
References Cited (Backward Citations)
US3791885A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-22 | 1979-06-23 | 1979-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-22 | 1983-06-23 | 1983-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-22 | 1987-06-23 | 1987-12-23 | $7700.00 | Window Closed / Lapsed |