Nonvolatile memory cell with vertical gate overlap and zero birds beaks

Claim 3

The device of claim 1, including a plurality of said cells, and the cells are arranged in a series of rows and columns, with the respective columns are separated by said regions of insulative material.

Claim 4

The device of claim 1, wherein the a second layer of dielectric material comprises an oxide-nitride-oxide (ONO) layer.

Claim 5

The device of claim 1, wherein the first and second conductive layers comprise conductive polysilicon.

Claim 6

The device of claim 1, wherein the first conductive layer comprises in-situ doped amorphous Si.

Claim 7

The device of claim 1, wherein the second conductive layers substantially fills the trench.

Claim 8

The device of claim 1, wherein dopant ions are implanted underlying the electrical isolation region adjacent the trench.

Claim 9

The device of claim 1, including a plurality of said cells, wherein the cells are arranged in a series of rows and columns, with the respective columns are separated by said isolation regions.

Claim 10

The device of claim 8, wherein each row has an associated word line electrically connecting the gate structures of each of the cells within the row, each column has an associated bit line electrically connecting the second semiconductor regions of each of the cells within the column, and the first semiconductor region of each cell within the array are electrically connected by a common line.

Claim 11

A memory device including at least one of cell, where: each cell comprises first, second and channel semiconductor regions and a selectively chargeable gate structure including a tunnel dielectric overlying the channel region, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the gate structure, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by movement of carriers from the gate structure through the tunnel dielectric to the first semiconductor region to remove the charge on the gate structure, and the cell is contiguous to regions of insulative material; the device improved wherein: the first, second and channel semiconductor regions are formed within substantially vertically sided trenches formed in the insulative material; and the selectively chargeable gate structure comprises: a first layer of dielectric, constituting the tunnel dielectric, disposed on the bottom of the trench, overlying the channel region; a first conductive layer disposed on the runnel dielectric, overlying the channel region and extending up the substantially vertical sides of the trench at least to the top thereof, generally conforming to the contours of the trench; a second layer of dielectric material disposed overlying the first conductive layer generally conforming to the contours of the trench within the trench interior and extending at least to the top thereof; and a second conductive layer disposed on the second dielectric, including surfaces opposing each of the bottom and substantially vertical portions of the first conductive layer, the second conductive layer extending to at least the top of the trench.

Claim 12

A memory device including at least one of cell, where: each cell comprises first, second and channel semiconductor regions and a selectively chargeable gate structure including a tunnel dielectric overlying the channel region, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the gate structure, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by movement of carriers from the gate structure through the tunnel dielectric to the first semiconductor region to remove the charge on the gate structure, and the cell is contiguous to regions of insulative material; the device improved wherein: the first, second and channel semiconductor regions are formed within substantially vertically sided trenches formed in the insulative material; and the selectively chargeable gate structure comprises: a first layer of dielectric, constituting the tunnel dielectric, disposed on the bottom of the trench, overlying the channel region; a first conductive layer disposed on the runnel dielectric, overlying the channel region and extending up the substantially vertical sides of the trench at least to the top thereof, generally conforming to the contours of the trench; a second layer of dielectric material disposed overlying the first conductive layer generally conforming to the contours of the trench within the trench interior and extending at least to the top thereof; and a second conductive layer disposed on the second dielectric, including surfaces opposing each of the bottom and substantially vertical portions of the first conductive layer, the second conductive layer extending to at least the top of the trench.

Claim 13

The device of claim 2, wherein each row has an associated word line electrically connecting the gate structures of each of the cells within the row, each column has an associated bit line electrically connecting the second semiconductor regions of each of the cells within the column, and the first semiconductor region of each cell within the array are electrically connected by a common line.

Claim 14

The device of claim 10, wherein the a second layer of dielectric material comprises an oxide-nitride-oxide (ONO) layer.

Claim 15

The device of claim 10, wherein the first and second conductive layers comprise conductive polysilicon.

Claim 16

The device of claim 10, wherein the first conductive layer comprises in-situ doped amorphous Silicon.

Claim 17

The device of claim 10, wherein the second conductive layers substantially fill the trenches.

Claim 18

The device of claim 2, wherein dopant ions are implanted underlying the insulative material between respective trenches.

Claim 19

The device of claim 2 further including channel stop regions underlying the insulative material between respective trenches.