System and method of computer operating mode control for power consumption reduction

Claim 2

In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; a method for controlling the operating mode of said computer system comprising: while operating in said first mode, monitoring said computer to detect execution of a predefined code thread, and generating a first-mode to second-mode transition command signal in response to said detecting execution of a predefined code thread; and changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal; said first operating mode characterized by maintaining clocking of said CPU at a first frequency; said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.

Claim 3

The method in claim 1, wherein said predefined code thread comprises an idle thread.

Claim 4

The method in claim 2, wherein said second predefined event comprises occurrence of a timer timeout condition a predetermined period of time after initiation of execution of said first idle thread.

Claim 5

The method in claim 2, wherein said second predefined event comprises occurrence of a predetermined timer timeout condition.

Claim 6

The method in claim 4, wherein said step of turning off at least one device comprises turning off clock to all devices except said memory.

Claim 7

The method in claim 1, wherein said execution of a predefined code thread comprises execution of a predefined code segment.

Claim 8

The method in claim 6, wherein said predefined code segment comprises an operating system call.

Claim 9

The method in claim 7, wherein said operating system call is an interrupt.

Claim 10

The method in claim 8, wherein said operating system is selected from the group consisting of a multi-tasking operating system, Microsoft Windows, Microsoft DOS, and combinations thereof.

Claim 11

The method in claim 8, wherein said interrupt comprises an idle state interrupt.

Claim 12

The method in claim 10, wherein said idle state interrupt is selected from the group consisting of DOS Idle Handler (Interrupt 28h), and DOS Idle Call (Interrupt 2Fh Function 1680).

Claim 13

The method in claim 8, wherein said interrupt comprises an idle handler.

Claim 14

The method in claim 12, wherein said idle handler enables background operations while the system waits for input.

Claim 15

The method in claim 12, wherein said idle handler is a operating system idle handler.

Claim 16

The method in claim 14, wherein said operating system idle handler comprises DOS Interrupt 28h.

Claim 17

The method in claim 14, wherein said operating system idle handler comprises DOS Multiplex Interrupt (Interrupt 2Fh).

Claim 18

The method in claim 14, wherein said operating system idle handler comprises DOS Idle Call (Interrupt 2Fh Function 1680).

Claim 19

The method in claim 12, wherein said idle handler comprises execution of an idle thread, and wherein execution of said idle thread communicates to other processes in said computer that the computer system is idle.

Claim 20

The method in claim 8, wherein said operating system call is an operating system multiplex interrupt and is used to monitor inter-process communications to identify idle class calls.

Claim 21

The method in claim 8, wherein said operating system call is an operating system multiplex interrupt and is used to monitor inter-process communications to identify operating system start-up and shut-down.

Claim 22

The method in claim 7, wherein said operating system call informs the system that the operating system is idle.

Claim 23

The method in claim 7, wherein said CPU is executing a plurality of threads and wherein each of said threads is in an idle state.

Claim 24

The method in claim 22, wherein said threads have an idle class priority such that they do not execute unless there are no threads having higher execution priority than said idle class priority.

Claim 25

The method in claim 22, wherein a keystroke check loop has an idle priority and is an indication of system idle.

Claim 26

The method in claim 22, wherein herein said thread is any thread that gives an indication that the system is at idle.

Claim 27

The method in claim 25, wherein said CPU generated command is selected from the group consisting of a system halt command, a system suspend command, and a system hibernate command.

Claim 28

The method in claim 25, wherein said CPU generated command is generated whenever an idle thread has been executing for more than a predetermined period of time.

Claim 29

The method in claim 1, wherein said first-mode to second-mode transition command slows or stops clocking of the CPU; and wherein said second-mode to third-mode transition command signal slows or stops clocking of other of said system devices and resources with the proviso that inputs required for maintenance of data stored in said memory are maintained.

Claim 30

The method in claim 1, wherein said second predetermined event comprises the occurrence of a second timer timeout.

Claim 31

The method in claim 1, further comprising the steps of: while operating in said third mode, monitoring said computer to detect occurrence or non-occurrence of a third predefined event, and generating a third-mode to first-mode transition command signal in response to said third event detection; and changing said operating mode from said third-mode to said first-mode in response to said third-mode to first-mode transition command signal.

Claim 32

The method in claim 30, wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt.

Claim 33

The method in claim 30, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event; and wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt.

Claim 34

The method in claim 30, further comprising the steps of: while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a fourth predefined event, and generating a second-mode to first-mode transition command signal in response to said fourth event detection; and changing said operating mode from said second-mode to said first-mode in response to said second-mode to first-mode transition command signal.

Claim 35

The method in claim 33, wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.

Claim 36

The method in claim 30, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event; and wherein said third event is selected from the group consisting of an occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt; and wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.

Claim 37

The method in claim 1, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event.

Claim 38

The method in claim 1, further comprising the step of directly commanding said system to any of said first-mode, second-mode, or third mode by a CPU command.

Claim 39

In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; a method for controlling the operating mode of said computer system comprising: while operating in said first mode, monitoring said computer to detect exceeding a threshold value for a statistical evaluation of active and idle process, and generating a first-mode to second-mode transition command signal in response to said detecting exceeding a threshold value for a statistical evaluation of active and idle process; and changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal; said first operating mode characterized by maintaining clocking of said CPU at a first frequency; said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.

Claim 40

In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; a method for controlling the operating mode of said computer system comprising: while operating in said first mode, monitoring said computer to detect exceeding a threshold value for a statistical evaluation of active and idle process, and generating a first-mode to second-mode transition command signal in response to said detecting exceeding a threshold value for a statistical evaluation of active and idle process; and changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal; said first operating mode characterized by maintaining clocking of said CPU at a first frequency; said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.

Claim 41

The method as in claim 38, wherein said idle process makes at least one function call.

Claim 42

The method as in claim 38, wherein said idle process is comprised of threads.

Claim 43

The method in claim 38, wherein said statistical evaluation comprises statistical evaluation of active and idle function calls.

Claim 44

In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling the system resources, at least one of said system devices and resources being operable in any one of three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; a method for controlling the operating mode of the computer system comprising the steps of: while operating in said first mode, monitoring said computer to detect completion of execution of all idle threads executing on said system, and generating a slow or stop processor clock command in response to said idle thread completion detection; while operating in said second mode wherein said CPU clock is slowed or stopped, receiving an interrupt from a timer circuit indicating occurrence of a predetermined timer time-out condition, and generating a slow or stop device command to slow or turn off clock signal to at least one of said devices in response to occurrence of said timeout condition; said first operating mode characterized by maintaining clocking of said CPU at a first clock frequency; said second operating mode characterized by clocking said CPU at a second clock frequency less than said first frequency or by not maintaining clocking of said CPU; and said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.

Claim 45

In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling the system resources, at least one of said system devices and resources being operable in any one of three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; a method for controlling the operating mode of the computer system comprising the steps of: while operating in said first mode, monitoring said computer to detect completion of execution of all idle threads executing on said system, and generating a slow or stop processor clock command in response to said idle thread completion detection; while operating in said second mode wherein said CPU clock is slowed or stopped, receiving an interrupt from a timer circuit indicating occurrence of a predetermined timer time-out condition, and generating a slow or stop device command to slow or turn off clock signal to at least one of said devices in response to occurrence of said timeout condition; said first operating mode characterized by maintaining clocking of said CPU at a first clock frequency; said second operating mode characterized by clocking said CPU at a second clock frequency less than said first frequency or by not maintaining clocking of said CPU; and said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.

Claim 46

The method in claim 42, further comprising the steps of: while operating in said third mode, monitoring said computer to detect occurrence or non-occurrence of a third predefined event, and generating a third-mode to first-mode transition command signal in response to said third event detection; and changing said operating mode from said third-mode to said first-mode in response to said third-mode to first-mode transition command signal.

Claim 47

The method in claim 43, wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and a predetermined hardware interrupt.

Claim 48

The method in claim 43, further comprising the steps of: while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a fourth predefined event, and generating a second-mode to first-mode transition command signal in response to said fourth event detection; and changing said operating mode from said second-mode to said first-mode in response to said second-mode to first-mode transition command signal.

Claim 49

The method in claim 45, wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.

Claim 50

The method in claim 42, wherein said first predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event; and wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event; and wherein said third event is selected from the group consisting of an occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt; and wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.

Claim 51

A computer system including as hardware a plurality of system resources including a processing unit responsive to a processor clock signal, a memory device, and an input/output device, and an operating system for controlling operation of said computer system, at least one of said system devices and resources being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; said computer system characterized in that said computer system further comprises: idle thread execution completion detection means for monitoring said computer system to detect completion of execution of all idle threads executing on said system while operating in said first mode; processor clock speed control means for slowing or stopping said processor clock signal in response to said idle thread execution completion detection; a timer circuit generating a timer-timeout signal indicating occurrence of a predetermined timer time-out condition; a device controller receiving said timer-timeout signal while operating in said second mode wherein said processor clock is slowed or stopped and generating a slow or stop device signal to slow or turn off clock signal to at least one of said devices in response to occurrence of said timer timeout condition; said first operating mode characterized by maintaining clocking of said processor at a first clock frequency; said second operating mode characterized by clocking said processor at a second clock frequency less than said first frequency or by not maintaining clocking of said processor; and said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.

Claim 52

A computer system including as hardware a plurality of system resources including a processing unit responsive to a processor clock signal, a memory device, and an input/output device, and an operating system for controlling operation of said computer system, at least one of said system devices and resources being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level; said computer system characterized in that said computer system further comprises: idle thread execution completion detection means for monitoring said computer system to detect completion of execution of all idle threads executing on said system while operating in said first mode; processor clock speed control means for slowing or stopping said processor clock signal in response to said idle thread execution completion detection; a timer circuit generating a timer-timeout signal indicating occurrence of a predetermined timer time-out condition; a device controller receiving said timer-timeout signal while operating in said second mode wherein said processor clock is slowed or stopped and generating a slow or stop device signal to slow or turn off clock signal to at least one of said devices in response to occurrence of said timer timeout condition; said first operating mode characterized by maintaining clocking of said processor at a first clock frequency; said second operating mode characterized by clocking said processor at a second clock frequency less than said first frequency or by not maintaining clocking of said processor; and said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.