Method and apparatus for providing breakpoints on a selectable address range

Claim 2

A processor comprising: a first storage area having stored therein a first address; a second storage area having stored therein a mask, said first address and said mask defining an address range; a data breakpoint storage area; a circuit receiving a second address that is a data address, said circuit coupled to said first storage area and said second storage area to receive said first address and said mask, said circuit writing said second address to said data breakpoint storage area if said second address is within said address range, said circuit having an output transmitting a signal to cause a debug event if said second address is within said address range; and an execution unit coupled to said output.

Claim 3

The processor of claim 1 further comprising a third storage area, coupled to said circuit, having stored therein an indication indicating whether said address range is enabled.

Claim 4

The processor of claim 2, said execution unit recognizing said debug event in response to said signal.

Claim 5

The processor of claim 1 further comprising: a third storage area, coupled to said circuit, having stored therein an indication for indicating whether said address range is applicable to data addresses, said circuit writing said second address and transmitting said signal only if said second address is within said address range and said indication indicates said address range is applicable to data addresses.

Claim 6

A processor comprising: a first storage area having stored therein an information defining an address range, said information capable of identifying said address range to be larger than 4 bytes; a circuit coupled to receive a first address, said circuit coupled to said first storage area, said circuit having an output transmitting a signal to cause a debug event if said first address is within said address range; a second storage area, coupled to said circuit, having stored therein an indication; a data breakpoint storage area, coupled to said circuit, having stored therein said first address if said first address is inside said address range and said indication indicates said address range is a data address range; and an execution unit coupled to said output.

Claim 7

A processor comprising: a first storage area having stored therein an information defining an address range, said information capable of identifying said address range to be larger than 4 bytes; a circuit coupled to receive a first address, said circuit coupled to said first storage area, said circuit having an output transmitting a signal to cause a debug event if said first address is within said address range; a second storage area, coupled to said circuit, having stored therein an indication; a data breakpoint storage area, coupled to said circuit, having stored therein said first address if said first address is inside said address range and said indication indicates said address range is a data address range; and an execution unit coupled to said output.

Claim 8

The processor of claim 5, said first storage area including a first register having stored therein a second address and a second register having stored therein a mask, said information including said first address and said mask.

Claim 9

The processor of claim 5, said execution unit recognizing said debug event in response to said signal.

Claim 10

A processor comprising: an address breakpoint means coupled to receive a first address generated to access data, said address breakpoint means for determining a debug breakpoint should be reported if each of a set of conditions is true, one of said set of conditions being if said first address is in an address range defined by a second address and a mask, said address breakpoint means also for storing said first address if it is determined said debug breakpoint should be reported; and an execution unit, coupled to said address breakpoint means, for recognizing said debug breakpoint if said address breakpoint means reports said debug breakpoint.

Claim 11

A processor comprising: an address breakpoint means coupled to receive a first address generated to access data, said address breakpoint means for determining a debug breakpoint should be reported if each of a set of conditions is true, one of said set of conditions being if said first address is in an address range defined by a second address and a mask, said address breakpoint means also for storing said first address if it is determined said debug breakpoint should be reported; and an execution unit, coupled to said address breakpoint means, for recognizing said debug breakpoint if said address breakpoint means reports said debug breakpoint.

Claim 12

The processor of claim 8, said address breakpoint means including, a first storage area for storing said second address; and a second storage area for storing said mask.

Claim 13

The processor of claim 8, further comprising: a first storage area for storing an indication identifying whether debug breakpoints are to be generated for addresses that are in said address range and that are generated to access data; and said address breakpoint means coupled to said first storage area, wherein another of said set of conditions is if said indication indicates that debug breakpoints are to be generated for addresses that are in said address range and that are generated to access data.

Claim 14

The processor of claim 8, wherein said set of conditions includes a single condition.

Claim 15

A computer system comprising: a storage area having stored therein an initialization routine and a debug handler; a processor coupled to said storage area including: a first storage area having stored therein a first address; a second storage area having stored therein a mask, said first address and said mask defining an address range, said first address and said mask having been stored by said processor executing said initialization routine; a third storage area a circuit receiving a second address that is a data address, said circuit coupled to said first storage area and said second storage area to receive said first address and said mask, said circuit writing said second address to said third storage area if said second address is within said address range, said circuit having an output transmitting a signal to cause a debug event if said second address is within said address range; and an execution unit coupled to said output executing said debug handler in response to said signal to provide information for debugging.

Claim 16

A computer system comprising: a storage area having stored therein an initialization routine and a debug handler; a processor coupled to said storage area including: a first storage area having stored therein a first address; a second storage area having stored therein a mask, said first address and said mask defining an address range, said first address and said mask having been stored by said processor executing said initialization routine; a third storage area a circuit receiving a second address that is a data address, said circuit coupled to said first storage area and said second storage area to receive said first address and said mask, said circuit writing said second address to said third storage area if said second address is within said address range, said circuit having an output transmitting a signal to cause a debug event if said second address is within said address range; and an execution unit coupled to said output executing said debug handler in response to said signal to provide information for debugging.

Claim 17

The computer system of claim 12 further comprising: a third storage area, coupled to said circuit, having stored therein an indication for indicating said address range is applicable to data addresses, said circuit writing said second address and transmitting said signal only if said second address is within said address range and said indication indicates said address range is applicable to data addresses.

Claim 20

The method of claim 14, said step of determining further comprising the steps of: masking said second address with said mask to generate a masked address; and comparing said masked address to said first address.

Claim 21

The method of claim 15, further comprising the steps of: storing a dynamic indication; and determining said dynamic indication indicates said address range is a data address range.

Claim 22

The method of claim 15, further comprising the step of executing said debug handler in response to said debug event.

Claim 23

In a computer system, a method for providing information useful in debugging, said method comprising the steps of: storing an information identifying an address range, said information capable of identifying an address range greater than 4 bytes; generating an address to access data as a result of executing a program; determining said address is in said address range; writing said address to a register for use in debugging; and causing a debug event.

Claim 24

In a computer system, a method for providing information useful in debugging, said method comprising the steps of: storing an information identifying an address range, said information capable of identifying an address range greater than 4 bytes; generating an address to access data as a result of executing a program; determining said address is in said address range; writing said address to a register for use in debugging; and causing a debug event.

Claim 25

The method of claim 18, further comprising the steps of: storing an indication identifying said address range as a data address range; and in response to said step of generating, determining said address range is a data address range based on said indication.

Claim 26

The method of claim 18, further comprising the step of executing a debug handler in response to said debug event.

Claim 27

A processor comprising: a first storage area configured to store a first address; a second storage area configured to store a mask, said first address and said mask defining an address range; a data breakpoint storage area; an address range breakpoint unit coupled to receive a second address generated to access either data or an instruction, said address range breakpoint unit coupled to said first storage area and said second storage area to receive said first address and said mask, said address range breakpoint unit configured to write said second address to said data breakpoint storage if each of a set of conditions is meet, said set of conditions including if said second address is within said address range and if said second address was generated to access data.

Claim 28

A processor comprising: a first storage area configured to store a first address; a second storage area configured to store a mask, said first address and said mask defining an address range; a data breakpoint storage area; an address range breakpoint unit coupled to receive a second address generated to access either data or an instruction, said address range breakpoint unit coupled to said first storage area and said second storage area to receive said first address and said mask, said address range breakpoint unit configured to write said second address to said data breakpoint storage if each of a set of conditions is meet, said set of conditions including if said second address is within said address range and if said second address was generated to access data.

Claim 29

The processor of claim 21 further comprising: a third storage area, coupled to said address range breakpoint unit, having stored therein an indication for designating said address range as being applicable to addresses generated to access data, said address range breakpoint unit coupled to receive said indication, said set of conditions including if said indication is currently designating said address range as applicable to addresses generated to access data.