US4409654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor adapted for interruption to an instruction stream
Assignee: Hitachi Ltd
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Filing: 1981-03-06
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Granted: 1983-10-11
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Expires: 2001-03-06
Abstract
Abstract An information processing system having an instruction unit for decoding each of successive instructions to generate an address of a next instruction, and additionally, when a branch instruction is decoded, a branch-to address of the decoded branch instruction. An execution unit sequentially executes the decoded instructions and a plurality of registers are provided for storing the next instruction address and the branch-to address. A pointer is generated to indicate one of the registers in which the next instruction address or the branch-to address is to be stored and the pointer is changed sequentially and cyclically in response to a first signal which is generated by the execution unit upon completion of execution of each decoded instruction or a second signal which is generated by the execution unit upon success in branch when a branch instruction is executed. Further provided is a delay circuit for receiving the pointer and generating it at a predetermined time delay. The delayed pointer is latched at a timing predetermined by the first and second signals and an interrupt signal produced, upon detection of an interrupt request, at a timing determined in dependence on the type of the interrupt request, and the instruction address used for a program status word is read out of one of the registers indicted by the latched pointer.
Inventors
- 👤 Kenichi Wada
- 👤 Naoki Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/30; G06F9/38; G06F9/3861; G06F9/461
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
327 words
An information processing system comprising: instruction means for sequentially decoding a plurality of instructions to generate the address of the next sequential instruction and to additionally generate, when the decoded instruction is a branch instruction, a branch-to address of said decoded branch instruction; means for generating an interrupt signal for various types of interrupt requests at a timing depending on the type of interrupt request; execution means connected to said instruction means for sequentially executing operations of said decoded instructions, when no interrupt signal is recieved from said interrupt generating means, including means for providing a first signal to said instruction means in response to completion of the operation of each of said decoded instructions for fetching from said instruction means a next sequential instruction address for an instruction to be next executed and means for providing a second signal to said instruction means, when a branch instruction is executed and the branch is successful, to fetch a branch-to address of said branch instruction from said instruction means; a plurality of registers; input pointer means for generating a pointer signal whose value indicates one of said registers, including means for storing any of said next sequential instruction address and said branch-to address, as fetched, in the register indicated by said pointer signal, and means for sequentially and cyclically changing said pointer value in response to one of said first and second signals for indicating said registers sequentially and cyclically; delay means connected to said input pointer means for receiving the pointer signal and producing it at a predetermined time delay; control means connected to receive said first, second and interrupt signals and for producing a third signal at a timing which is determined by said first, second and interrupt signals; latch means for latching said delayed pointer signal in response to said third signal; and means for reading the address out of one of said registers indicated by the delay pointer signal latched by said latch means.
Claim 2
Dependent Claim
327 words
An information processing system comprising: instruction means for sequentially decoding a plurality of instructions to generate the address of the next sequential instruction and to additionally generate, when the decoded instruction is a branch instruction, a branch-to address of said decoded branch instruction; means for generating an interrupt signal for various types of interrupt requests at a timing depending on the type of interrupt request; execution means connected to said instruction means for sequentially executing operations of said decoded instructions, when no interrupt signal is recieved from said interrupt generating means, including means for providing a first signal to said instruction means in response to completion of the operation of each of said decoded instructions for fetching from said instruction means a next sequential instruction address for an instruction to be next executed and means for providing a second signal to said instruction means, when a branch instruction is executed and the branch is successful, to fetch a branch-to address of said branch instruction from said instruction means; a plurality of registers; input pointer means for generating a pointer signal whose value indicates one of said registers, including means for storing any of said next sequential instruction address and said branch-to address, as fetched, in the register indicated by said pointer signal, and means for sequentially and cyclically changing said pointer value in response to one of said first and second signals for indicating said registers sequentially and cyclically; delay means connected to said input pointer means for receiving the pointer signal and producing it at a predetermined time delay; control means connected to receive said first, second and interrupt signals and for producing a third signal at a timing which is determined by said first, second and interrupt signals; latch means for latching said delayed pointer signal in response to said third signal; and means for reading the address out of one of said registers indicated by the delay pointer signal latched by said latch means.
Claim 3
Dependent Claim
53 words
An information processing system according to claim 1, wherein said control means comprises second delay means for receiving said first, second and interrupt signals and for reproducing them at predetermined time delays, respectively, and means for producing said third signal when said delayed first, second and interrupt signals satisfy a predetermined logical condition.
Claim 4
Dependent Claim
75 words
An information processing system according to claim 2, wherein said interrupt request detecting means produces, as said interrupt signal, a first interrupt signal which is invariable regardless of the type of the detected interrupt request and a second interrupt signal which is variable depending on the type of the detected interrupt request, and said second delay means includes means for receiving said first and second interrupt signals and for reproducing them at different time delays.
Claim 5
Dependent Claim
85 words
An information processing system according to claim 2, wherein said control means includes means for producing a fourth signal at a timing which is determined by said first and interrupt signals, said latch means being further responsive to said fourth signal to latch said delayed pointer signal, and wherein the values of said delayed pointer signal latched in response to said third and fourth signal, respectively, indicate the registers which store instruction addresses used for a program status word and a program event record, respectively.
Claim 6
Dependent Claim
74 words
An information processing system according to claim 4, wherein said control means further comprises second delay means for receiving said first, second and interrupt signals and for reproducing them at predetermined time delays respectively; means for producing said third signal when said delayed first, second and interrupt signals satisfy a predetermined first logical condition and means for producing said fourth signal when said delayed first and interrupt signals satisfy a predetermined second logical condition.
Claim 7
Dependent Claim
78 words
An information producing system according to claim 5, wherein said interrupt request detecting means includes means for producing, as said interrupt signal, a first interrupt signal which is invariable regardless of the type of the detected interrupt request and a second interrupt signal which is variable depending on the type of the detected interrupt request, and said second delay means includes means for receiving said first and second interrupt signals and for reproducing them at different time delays.
References Cited (Backward Citations)
US4161026A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |