Apparatus using address of a predetermined preceding instruction and target instruction address stored in history table to prefetch target instruction

Claim 2

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is an unconditional branch instruction, an address of a sixth one of the instructions, to which said fifth instruction is branched, and an address of a preceding instruction preceding to said fourth instruction, when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; and a pre-branch unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (i) outputting the address of said sixth instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said preceding instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction.

Claim 3

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is an unconditional branch instruction, a pre-fetched instruction code of a sixth one of the instructions, to which said fifth instruction is branched, an address used for pre-fetching an instruction succeeding to said sixth instruction, and an address of said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; and a pre-branch unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (i) outputting the instruction code of said sixth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction.

Claim 4

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is an unconditional branch instruction, a pre-fetched instruction code of a sixth one of the instructions, to which said fifth instruction is branched, an address used for pre-fetching an instruction succeeding to said sixth instruction, and an address of said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; and a pre-branch unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (i) outputting the instruction code of said sixth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction.

Claim 5

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, (i) if a fifth one of the instructions succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instructions in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, an address of a sixth one of the instructions which is succeeding to said fifth instruction and being processed in said instruction decoding unit, a condition code for judging the conditional branch of said fifth instruction, an address of a preceding instruction preceding said fourth instruction, and an address of said seventh instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, an address of said seventh instruction, a condition code for judging the conditional branch of said fifth instruction, an address of a preceding instruction preceding to said fourth instruction, and an address of said sixth instruction, when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (a) outputting the address of said sixth or seventh instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (b) when the address of said preceding instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a branch verification unit for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said sixth or seventh instruction and executes said seventh or sixth instruction respectively after execution of said fourth instruction.

Claim 6

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, (i) if a fifth one of the instructions succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instructions in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, an address of a sixth one of the instructions which is succeeding to said fifth instruction and being processed in said instruction decoding unit, a condition code for judging the conditional branch of said fifth instruction, an address of a preceding instruction preceding said fourth instruction, and an address of said seventh instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, an address of said seventh instruction, a condition code for judging the conditional branch of said fifth instruction, an address of a preceding instruction preceding to said fourth instruction, and an address of said sixth instruction, when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (a) outputting the address of said sixth or seventh instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (b) when the address of said preceding instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a branch verification unit for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said sixth or seventh instruction and executes said seventh or sixth instruction respectively after execution of said fourth instruction.

Claim 7

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instructions in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, a pre-fetched instruction code of a sixth one of the instructions which is succeeding to said fifth instructions, an address used for pre-fetching an instruction succeeding to said sixth instruction, a condition code for judging the conditional branch of said fifth instruction, an address of said fourth instruction and an address of said seventh instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, a pre-fetched instruction code of said seventh instruction, an address used for pre-fetching an instruction succeeding to said seventh instruction, a condition code for judging the conditional branch of said fifth instruction, an address of said fourth instruction, and an address of said sixth instruction, when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (a) outputting the instruction code of said sixth or seventh instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth or seventh instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (b) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a branch verification unit for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said sixth or seventh instruction and executes said seventh or sixth instruction respectively after execution of said fourth instruction.

Claim 8

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a conditional branch instruction which may branch to a seventh one of the instructions in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is not taken, a pre-fetched instruction code of a sixth one of the instructions which is succeeding to said fifth instructions, an address used for pre-fetching an instruction succeeding to said sixth instruction, a condition code for judging the conditional branch of said fifth instruction, an address of said fourth instruction and an address of said seventh instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a conditional branch instruction which may branch to said seventh instruction in accordance with an execution result of said fourth instruction and a conditional branch of said fifth instruction is taken, a pre-fetched instruction code of said seventh instruction, an address used for pre-fetching an instruction succeeding to said seventh instruction, a condition code for judging the conditional branch of said fifth instruction, an address of said fourth instruction, and an address of said sixth instruction, when said fifth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (a) outputting the instruction code of said sixth or seventh instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth or seventh instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth or seventh instruction after execution of said fourth instruction and (b) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a branch verification unit for verifying, while said instruction execution unit executes said sixth or seventh instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said sixth or seventh instruction and executes said seventh or sixth instruction respectively after execution of said fourth instruction.

Claim 9

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data, an address of a sixth one of the instructions which is succeeding to said fifth instruction and being processed in said instruction decoding unit, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, and an address of a preceding instruction preceding to said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; a compare instruction remove unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (i) outputting the address of said sixth instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said preceding instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said sixth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit.

Claim 10

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data, an address of a sixth one of the instructions which is succeeding to said fifth instruction and being processed in said instruction decoding unit, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, and an address of a preceding instruction preceding to said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; a compare instruction remove unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (i) outputting the address of said sixth instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said preceding instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said sixth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit.

Claim 11

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data, a pre-fetched instruction code of a sixth one of the instructions which is succeeding to said fifth instruction, an address used for pre-fetching an instruction succeeding to said sixth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, and an address of said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; a compare instruction remove unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (i) outputting the instruction code of said sixth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said sixth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit.

Claim 12

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data, a pre-fetched instruction code of a sixth one of the instructions which is succeeding to said fifth instruction, an address used for pre-fetching an instruction succeeding to said sixth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, and an address of said fourth instruction, when said fifth instruction is executed at least in a first cycle of cyclic executions of said instructions; a compare instruction remove unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (i) outputting the instruction code of said sixth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said sixth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said sixth instruction after execution of said fourth instruction and (ii) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; and a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said sixth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit.

Claim 13

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data and a sixth one of the instructions succeeding to said fifth instruction is a conditional branch instruction which may branch to an eighth one of the instructions in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is not taken, an address of a seventh one of the instructions which is succeeding to said sixth instruction and being processed in said instruction decoding unit, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, and address of a preceding instruction preceding to said fourth instruction, and an address of said eighth instruction, when said sixth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a comparison instruction which compares two general register contents or one general register content with immediate data and said sixth instruction is a conditional branch instruction which may branch to said eighth instruction in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is taken, an address of said eighth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of a preceding instruction preceding to said fourth instruction, and an address of said seventh instruction, when said sixth instruction is executed at least in a first cycle of the cyclic executions said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (a) outputting the address of said seventh or eighth instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said seventh or eighth instruction after execution of said fourth instruction and (b) when the address of said preceding instruction is not stored in said history storage unit, causing instruction execution unit to execute said fifth instruction after execution of said fourth instruction; a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said seventh or eighth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit; and a branch verification unit for verifying, while said instruction execution unit executes said seventh or eighth instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the comparison result received from said comparison unit and the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said seventh or eighth instruction and executes said eighth or seventh instruction respectively after execution of said fourth instruction.

Claim 14

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction which compares two general register contents or one general register content with immediate data and a sixth one of the instructions succeeding to said fifth instruction is a conditional branch instruction which may branch to an eighth one of the instructions in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is not taken, an address of a seventh one of the instructions which is succeeding to said sixth instruction and being processed in said instruction decoding unit, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, and address of a preceding instruction preceding to said fourth instruction, and an address of said eighth instruction, when said sixth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a comparison instruction which compares two general register contents or one general register content with immediate data and said sixth instruction is a conditional branch instruction which may branch to said eighth instruction in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is taken, an address of said eighth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of a preceding instruction preceding to said fourth instruction, and an address of said seventh instruction, when said sixth instruction is executed at least in a first cycle of the cyclic executions said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said preceding instruction, and (a) outputting the address of said seventh or eighth instruction to said instruction pre-fetch unit, when the address of said preceding instruction is stored in said history storage unit, so that said instruction execution unit executes said seventh or eighth instruction after execution of said fourth instruction and (b) when the address of said preceding instruction is not stored in said history storage unit, causing instruction execution unit to execute said fifth instruction after execution of said fourth instruction; a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said seventh or eighth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit; and a branch verification unit for verifying, while said instruction execution unit executes said seventh or eighth instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the comparison result received from said comparison unit and the condition code in said history storage unit, and outputting a signal, when an instruction now executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said seventh or eighth instruction and executes said eighth or seventh instruction respectively after execution of said fourth instruction.

Claim 15

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction while compares two general register contents or one general register content with immediate data and a sixth one of the instructions succeeding to said fifth instruction is a conditional branch instruction which may branch to an eighth one of the instructions in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is not taken, a pre-fetched instruction code of a seventh one of the instructions which is succeeding to said sixth instruction, an address used for pre-fetching an instruction succeeding to said seventh instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of said fourth instruction, and an address of said eighth instruction, when said sixth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a comparison instruction which compares two general register contents or one general register content with immediate data and said sixth instruction is a conditional branch instruction which may branch to said eighth instruction in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is taken, a pre-fetched instruction code of said eighth instruction, an address used for pre-fetching an instruction succeeding to said eighth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of said fourth instruction, and an address of said seventh instruction, when said sixth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (a) outputting the instruction code of said seventh or eighth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said seventh or eighth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said seventh or eighth instruction after execution of said fourth instruction and (b) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said seventh or eighth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit; and a branch verification unit for verifying, while said instruction execution unit executes said seventh or eighth instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the comparison result received from said comparison unit and the condition code in said history storage unit, and outputting a signal, when an instruction currently being executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said seventh or eighth instruction and executes said eighth or seventh instruction respectively after execution of said fourth instruction.

Claim 16

A data processor for executing a plurality of predetermined instructions cyclically, comprising: an instruction execution unit having at least a general register for executing a first one of the instructions; an instruction decoding unit for decoding a second one of the instructions following said first instruction while said instruction execution unit is executing said first instruction; an instruction pre-fetch unit for pre-fetching a third one of the instructions following said second instruction while said instruction decoding unit is decoding said second instruction; a history storage unit for (i) storing, if a fifth one of the instructions succeeding to a fourth one of the instructions is a comparison instruction while compares two general register contents or one general register content with immediate data and a sixth one of the instructions succeeding to said fifth instruction is a conditional branch instruction which may branch to an eighth one of the instructions in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is not taken, a pre-fetched instruction code of a seventh one of the instructions which is succeeding to said sixth instruction, an address used for pre-fetching an instruction succeeding to said seventh instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of said fourth instruction, and an address of said eighth instruction, when said sixth instruction is executed at least in a first cycle of cyclic executions of said instructions, and (ii) if said fifth instruction is a comparison instruction which compares two general register contents or one general register content with immediate data and said sixth instruction is a conditional branch instruction which may branch to said eighth instruction in accordance with an execution result of said fifth instruction and a conditional branch of said sixth instruction is taken, a pre-fetched instruction code of said eighth instruction, an address used for pre-fetching an instruction succeeding to said eighth instruction, an information designating said general register contents or said immediate data for a comparison of said fifth instruction, a condition code for judging a conditional branch of said sixth instruction, an address of said fourth instruction, and an address of said seventh instruction, when said sixth instruction is executed at least in a first cycle of the cyclic executions of said instructions; a branch prediction unit for searching said history storage unit for its contents, while said instruction decoding unit decodes said fourth instruction, and (a) outputting the instruction code of said seventh or eighth instruction to said instruction decoding unit and the address used for pre-fetching the instruction succeeding to said seventh or eighth instruction to said instruction pre-fetch unit, when the address of said fourth instruction is stored in said history storage unit, so that said instruction execution unit executes said seventh or eighth instruction after execution of said fourth instruction and (b) when the address of said fourth instruction is not stored in said history storage unit, causing said instruction execution unit to execute said fifth instruction after execution of said fourth instruction; a comparison unit for carrying out the comparison of said fifth instruction, while said instruction execution unit executes said seventh or eighth instruction, by using the information in said history storage unit and outputting a comparison result to said instruction execution unit; and a branch verification unit for verifying, while said instruction execution unit executes said seventh or eighth instruction, whether an instruction currently being executed by said instruction execution unit is an instruction to be executed after said fourth instruction, in accordance with the comparison result received from said comparison unit and the condition code in said history storage unit, and outputting a signal, when an instruction currently being executed is not an instruction to be executed, to said instruction execution unit and said instruction decoding unit and said instruction pre-fetch unit so that said instruction execution unit cancels an execution result of said seventh or eighth instruction and executes said eighth or seventh instruction respectively after execution of said fourth instruction.