Preceding instruction address based branch prediction in a pipelined processor

Claim 2

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means for accessing the branch prediction information for said given branch instruction, prior to decoding the given branch instruction, with the instruction address of a selected instruction that precedes the given branch instruction in the sequence of instructions.

Claim 3

The invention of claim 1 further comprising: means for updating the branch prediction table information when said given branch instruction is executed.

Claim 4

The invention of claim 2 further comprising: means for generating the destination address for the given branch instruction if the accessed branch prediction information predicts that the branch condition of the given branch instruction will be established.

Claim 5

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means for accessing the branch prediction information for said given branch instruction, prior to decoding the given branch instruction, with the instruction address of a selected instruction that precedes the given branch instruction in the sequence of instructions; and means for updating the branch prediction table information when said given branch instructions is executed.

Claim 6

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means for accessing the branch prediction information for said given branch instruction, prior to decoding the given branch instruction, with the instruction address of a selected instruction that precedes the given branch instruction in the sequence of instructions; and means for updating the branch prediction table information when said given branch instructions is executed.

Claim 7

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means for accessing the branch prediction information for said given branch instruction, prior to decoding the given branch instruction, with the instruction address of a selected instruction that precedes the given branch instruction in the sequence of instructions; and means for generating the destination address for the given branch instruction if the accessed branch prediction information predicts that the branch condition of the given branch instruction will be established.

Claim 8

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means for accessing the branch prediction information for said given branch instruction, prior to decoding the given branch instruction, with the instruction address of a selected instruction that precedes the given branch instruction in the sequence of instructions; and means for generating the destination address for the given branch instruction if the accessed branch prediction information predicts that the branch condition of the given branch instruction will be established.

Claim 9

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means, at the instruction decoder, for calculating the address of a selected instruction currently being decoded; means for utilizing said calculated address to access the branch prediction table information for said given branch instruction, where said given branch instruction follows said selected instruction in the sequence of instructions.

Claim 10

In a data processor of the type having a pipeline system for executing pipeline processing on a sequence of instructions, including branch instructions, corresponding to associated instruction addresses and having a prefetch unit for preliminary fetching instructions corresponding to instruction addresses provided thereto, an instruction decoder that receives an instruction from said prefetch unit and that decodes the received instruction, and an instruction execution unit that receives the decoded instruction from said instruction decoder and executes said instruction, a branch prediction system comprising: a branch prediction unit, having a branch prediction table with branch prediction information stored therein for predicting whether the branch condition of a given branch instruction will be established; means, at the instruction decoder, for calculating the address of a selected instruction currently being decoded; means for utilizing said calculated address to access the branch prediction table information for said given branch instruction, where said given branch instruction follows said selected instruction in the sequence of instructions.