Instruction pre-fetch microprocessor interrupt system

Claim 2

In a data processing system which includes: a microprocessor apparatus operable in instruction cycles between a running state wherein instructions are processed and a wait state wherein no instructions are processed by the microprocessor and wherein microprocessor instructions generate enable and disable interrupt commands, the microprocessor generating instructions for changing page information, performing storage operations, branch and link operations and return operations; a page storage unit for storing page information which is set and reset to a zero state by microprocessor instructions; a storage unit for storing data and instructions; an arithmetic and logic unit having associated status bits which are set and reset to a zero state by microprocessor instructions; a plurality of peripheral devices connected to the microprocessor, the plurality of peripheral devices generating interrupt requests to the microprocessor for operating in an interrupt cycle; and the system operating in a pre-fetch mode wherein a next succeeding instruction is fetched from the storage unit while a current instruction is being executed, an interrupt system for processing interrupt requests received by the microprocessor from the plurality of peripheral devices cmprising: instruction address register means coupled to the storage unit for holding the next succeeding address to be pre-fetched in a sequence of instructions and operable to be updated to the value of the next succeeding address; storage address register means coupled to said instruction address register means and coupled to the storage unit for holding the next succeeding instruction address during execution of the current instruction; first latch means coupled to the microprocessor for receiving and storing an interrupt request received from the microprocessor and generated by one of the plurality of peripheral devices; second latch means coupled to the storage unit and controlled by the microprocessor instructions for enabling and disabling interrupts that are received from the microprocessor when said first latch means has stored an interrupt request from the microprocessor; interrupt link register means coupled to said instruction address register means for storing the values stored in said instruction address register means when an interrupt request is generated from one of the plurality of peripheral devices to the microprocessor; interrupt means coupled to said first and second latch means for inhibiting the updating of the value of said instruction address register means to a next succeeding instruction to be pre-fetched during the first succeeding cycle following storage of an interrupt request by said first latch means; means coupled to said first and second latch means and responsive to a successful branch operation resulting from the next instruction stored in said instruction address register for inhibiting operation of said interrupt means until completion of the successful branch operation; and means coupled to said first and second latch means and responsive to storage of data in the storage unit for inhibiting operation of said interrupt means until completion of the storage cycle.

Claim 3

The interrupt system of claim 1 and further including page register means coupled to said interrupt means and to said interrupt link register means for storing page information, such that said interrupt link register means stores values of said page register means stored therein when an interrupt request is generated by one of the plurality of peripheral devices to the microprocessor, transfer means coupled to said page register means and to said interrupt link register means for transferring the contents of said page register means to said interrupt link register means upon execution of an interrupt cycle by the microprocessor, and restore means coupled to said page register means and to said interrupt link register means for restoring the contents of said page register means upon completion of execution of the interrupt cycle, such that said page register means is available for use after the interrupt cycle has been completed by the microprocessor.

Claim 4

The interrupt system of claim 1 and further including arithmetic and logic unit status bits register means coupled to the arithmetic and logic unit for storing status bits, such that said interrupt link register means stores values of said arithmetic and logic unit status bits register means stored therein when an interrupt request is generated by one of the plurality of peripheral devices to the microprocessor, transfer means coupled to said arithmetic and logic unit status bits register means and to said interrupt link register means for transferring the contents of said arithmetic and logic unit status bits register means to said interrupt link register means upon execution of an interrupt cycle by the microprocessor; and restore means coupled to said arithmetic and logic unit status bits register means and to said interrupt link register means for restoring the contents of said arithmetic and logic unit status bits register means upon completion of execution of the interrupt cycle, such that said arithmetic and logic unit status bits register means is available for use after the interrupt cycle has been completed by the microprocessor.

Claim 5

The interrupt system of claim 1 wherein said interrupt means includes means for forcing an interrupt address from the storage unit to said storage address register means for accessing the next instruction from the storage unit for use in the next succeeding cycle of the microprocessor.

Claim 6

The interrupt system of claim 1 wherein said interrupt means includes means for storing in said interrupt link register the instruction address and page information stored in the page storage unit when the interrupt was executed by the microprocessor.

Claim 7

The interrupt system of claim 1 wherein said interrupt means includes means for storing in said interrupt link register the arithmetic and logic unit status bits stored in the arithmetic and logic unit when the interrupt was executed by the microprocessor.

Claim 8

The interrupt system of claim 1 wherein said interrupt means includes means for resetting of the contents of the page information stored in the page storage unit to a zero state.

Claim 9

The interrupt system of claim 1 wherein said interrupt means includes means for resetting of the contents of the arithmetic and logic unit status bits stored in the arithmetic and logic unit to a zero state.

Claim 10

The interrupt system of claim 1 wherein the microprocessor includes clock means and further includes: means for actuating the microprocessor clock means when an interrupt request occurs and the interrupt request has been enabled when the microprocessor is in the wait state.

Claim 11

In a data processing system which includes: a microprocessor apparatus operable in instruction cycles between a running state wherein instructions are processed and a wait state wherein no instructions are processed by the microprocessor and wherein microprocessor instructions generate enable and disable interrupt commands, the microprocessor generating instructions for changing page information, performing storage operations, branch and link operations and return operations; a page storage unit for storing page information which is set and reset to a zero state by microprocessor instructions; a storage unit for storing data and instructions; an arithmetic and logic unit having associated status bits which are set and reset to a zero state by microprocessor instructions; a plurality of peripheral devices connected to the microprocessor, the plurality of peripheral devices generating interrupt requests to the microprocessor for operating in an interrupt cycle; and the system operating in a pre-fetch mode wherein a next succeeding instruction is fetched from the storage unit while a current instruction is being executed, an interrupt system for processing interrupt requests received by the microprocessor from the plurality of peripheral devices comprising: instruction address register means coupled to the storage unit for holding the next succeeding address to be pre-fetched in a sequence of instructions and operable to be updated to the value of the next succeeding address; storage address register means coupled to said instruction address register means and coupled to the storage unit for holding the next succeeding instruction address during execution of the current instruction; first latch means coupled to the microprocessor for receiving and storing an interrupt request received from the microprocessor and generated by one of the plurality of peripheral devices; second latch means coupled to the storage unit and controlled by the microprocessor instructions for enabling and disabling interrupts that are received from the microprocessor when said first latch means has stored an interrupt request from the microprocessor; interrupt link register means coupled to said instruction address register means for storing the values stored in said instruction address register means and for storing page information stored in the page storage unit when an interrupt request is generated from one of the plurality of peripheral devices to the microprocessor; interrupt means coupled to said first and second latch means for inhibiting the updating of the value of said instruction address register means to a next succeeding instruction to be pre-fetched during the first succeeding cycle following storage of an interrupt request by said first latch means; said interrupt means includes means for forcing an interrupt address from the storage unit to said storage address register means for accessing the next instruction from the storage unit for use in the next succeeding cycle of the microprocessor; said interrupt means includes means for storing in said interrupt link register the instruction address and page information stored in the page storage unit when the interrupt was executed by the microprocessor; said interrupt means includes means for storing in said interrupt link register the arithmetic and logic unit status bits stored in the arithmetic and logic unit when the interrupt was executed by the microprocessor; means coupled to said first and second latch means and responsive to a successful branch operation resulting from the next instruction stored in said instruction address register for inhibiting operation of said interrupt means until completion of the successful branch operation; and means coupled to said first and second latch means and responsive to storage of data in the storage unit for inhibiting operation of said interrupt means until completion of the storage cycle.

Claim 12

In a data processing system which includes: a microprocessor apparatus operable in instruction cycles between a running state wherein instructions are processed and a wait state wherein no instructions are processed by the microprocessor and wherein microprocessor instructions generate enable and disable interrupt commands, the microprocessor generating instructions for changing page information, performing storage operations, branch and link operations and return operations; a page storage unit for storing page information which is set and reset to a zero state by microprocessor instructions; a storage unit for storing data and instructions; an arithmetic and logic unit having associated status bits which are set and reset to a zero state by microprocessor instructions; a plurality of peripheral devices connected to the microprocessor, the plurality of peripheral devices generating interrupt requests to the microprocessor for operating in an interrupt cycle; and the system operating in a pre-fetch mode wherein a next succeeding instruction is fetched from the storage unit while a current instruction is being executed, an interrupt system for processing interrupt requests received by the microprocessor from the plurality of peripheral devices comprising: instruction address register means coupled to the storage unit for holding the next succeeding address to be pre-fetched in a sequence of instructions and operable to be updated to the value of the next succeeding address; storage address register means coupled to said instruction address register means and coupled to the storage unit for holding the next succeeding instruction address during execution of the current instruction; first latch means coupled to the microprocessor for receiving and storing an interrupt request received from the microprocessor and generated by one of the plurality of peripheral devices; second latch means coupled to the storage unit and controlled by the microprocessor instructions for enabling and disabling interrupts that are received from the microprocessor when said first latch means has stored an interrupt request from the microprocessor; interrupt link register means coupled to said instruction address register means for storing the values stored in said instruction address register means and for storing page information stored in the page storage unit when an interrupt request is generated from one of the plurality of peripheral devices to the microprocessor; interrupt means coupled to said first and second latch means for inhibiting the updating of the value of said instruction address register means to a next succeeding instruction to be pre-fetched during the first succeeding cycle following storage of an interrupt request by said first latch means; said interrupt means includes means for forcing an interrupt address from the storage unit to said storage address register means for accessing the next instruction from the storage unit for use in the next succeeding cycle of the microprocessor; said interrupt means includes means for storing in said interrupt link register the instruction address and page information stored in the page storage unit when the interrupt was executed by the microprocessor; said interrupt means includes means for storing in said interrupt link register the arithmetic and logic unit status bits stored in the arithmetic and logic unit when the interrupt was executed by the microprocessor; means coupled to said first and second latch means and responsive to a successful branch operation resulting from the next instruction stored in said instruction address register for inhibiting operation of said interrupt means until completion of the successful branch operation; and means coupled to said first and second latch means and responsive to storage of data in the storage unit for inhibiting operation of said interrupt means until completion of the storage cycle.

Claim 13

The interrupt system of claim 10 wherein said interrupt link register means stores values of the arithmetic and logic unit status bits stored in the arithmetic and logic unit when an interrupt request occurs from one of the plurality of peripheral devices to the microprocessor.

Claim 14

The interrupt system of claim 11 wherein said interrupt means includes means for resetting of the contents of the arithmetic and logic unit status bits stored in the arithmetic and logic unit to a zero state.

Claim 15

The interrupt system of claim 12 wherein said interrupt means includes means for resetting of the contents of the page information stored in the page storage unit to a zero state.

Claim 16

The interrupt system of claim 13 wherein the microprocessor includes clock means and further includes: means for actuating the microprocessor clock means when an interrupt request occurs and the interrupt request is enabled when the microprocessor is in the wait state.

Claim 17

The interrupt system of claim 10 and further including: a plurality of register means for storing information coupled to said interrupt means; transfer means coupled to said plurality of register means and said interrupt link register means for transferring said information stored in said plurality of register means to said interrupt link register means upon the execution of an interrupt cycle by the microprocessor; restore means coupled to said plurality of register means and said interrupt link register means for restoring said information stored in said plurality of register means upon completion of execution of the interrupt cycle, such that said plurality of register means are available for use after the interrupt cycle has been completed by the microprocessor; means coupled to said interrupt means for recording each execution of each branch and link instruction and each return instruction generated by the microprocessor from the storage unit while the microprocessor operates in the interrupt cycle; and means coupled to said interrupt means for determining the difference in the number of branch and link instructions and return instructions generated by the microprocessor, such that when the number of return instructions is greater than the number of branch and link instructions the interrupt cycle is completed and, the return instruction causes the information stored in said plurality of register means to be automatically restored from said interrupt link register means to said plurality of register means.

Claim 18

The interrupt system of claim 15 wherein said plurality of register means includes page register means for storing page information, such that said interrupt link register means stores values of said page register means stored therein when an interrupt request occurred from one of the plurality of peripheral devices to the microprocessor; said transfer means transfers the contents of said page register means to said interrupt link register means upon initiation of an interrupt cycle; and said restore means restores the contents of said page register means upon completion of execution of the interrupt cycle, such that said page register means is available for use after the interrupt cycle has been completed by the microprocessor.

Claim 19

The interrupt system of claim 15 wherein said plurality of register means includes arithmetic and logic unit status bits register means for storing status bits, such that said interrupt link register means stores values of said arithmetic and logic unit status bits register means stored therein when an interrupt request occurred from one of the plurality of peripheral devices to the microprocessor; said transfer means transfers the contents of said arithmetic and logic unit status bits register means to said interrupt link register means upon initiation of an interrupt cycle; and said restore means restores the contents of said arithmetic and logic unit status bits register means upon completion of execution of the interrupt cycle; such that said arithmetic and logic unit status bits register means is available for use after the interrupt cycle has been completed by the microprocessor.

Claim 20

In a data processing system which includes: a microprocessor apparatus operable in instruction cycles between a running state wherein instructions are processed and a wait state wherein no instructions are processed by the microprocessor and wherein microprocessor instructions generate enable and disable interrupt commands, the microprocessor generating instructions for changing page information, performing storage operations, branch and link operations and return operations; a page storage unit for storing page information which is set and reset to a zero state by microprocessor instructions; a storage unit for storing data and instructions; an arithmetic and logic unit having associated status bits which are set and reset to a zero state by microprocessor instructions; a plurality of peripheral devices connected to the microprocessor, the plurality of peripheral devices generating interrupt requests to the microprocessor for operating in an interrupt cycle; and the system operating in a pre-fetch mode wherein a next succeeding instruction is fetched from the storage unit while a current instruction is being executed, an interrupt system for processing interrupt requests received by the microprocessor from the plurality of peripheral devices comprising: instruction address register means coupled to the storage unit for holding the next succeeding address to be pre-fetched in a sequence of instructions and operable to be updated to the value of the next succeeding address; storage address register means coupled to said instruction address register means and coupled to the storage unit for holding the next succeeding instruction address during execution of the current instruction; first latch means coupled to the microprocessor for receiving and storing an interrupt request received from the microprocessor and generated by one of the plurality of peripheral devices; second latch means coupled to the storage unit and controlled by the microprocessor instructions for enabling and disabling interrupts that are received from the microprocessor when said first latch means has stored an interrupt request from the microprocessor; interrupt link register means coupled to said instruction address register means for storing the values stored in said instruction address register means when an interrupt request is generated from one of the plurality of peripheral devices to the microprocessor; interrupt means coupled to said first and second latch means for inhibiting the updating of the value of said instruction address register means to a next succeeding instruction to be pre-fetched during the first succeeding cycle following storage of an interrupt request by said first latch means; means coupled to said first and second latch means and responsive to a successful branch operation resulting from the next instruction stored in said instruction address register for inhibiting operation of said interrupt means until completion of said successful branch operation; means coupled to said first and second latch means and responsive to storage of data in the storage unit for inhibiting operation of said interrupt means until completion of the storage cycle; transfer means coupled to said instruction address register means and to said interrupt link register means for transferring the contents of said instruction address register means to said interrupt link register means upon the processing of an interrupt cycle by the microprocessor; restore means coupled to said intruction address register means and to said interrupt link register means for restoring the contents of said instruction address register means upon completion of execution of the interrupt cycle, such that said instruction address register means is available for use after the interrupt cycle has been completed by the microprocessor; means coupled to said interrupt means for recording each execution of each branch and link instruction and each return instruction generated by the microprocessor from the stroage unit while the microprocessor operates in the interrupt cycle; and means coupled to said interrupt means for determining the difference in the number of branch and link instructions and return instructions generated by the microprocessor, such that when the number of return instructions is greater than the number of branch and link instructions the interrupt cycle is completed and the return instruction causes the information stored in said interrupt link register means to be automatically restored from said interrupt link register means to said instruction address register.

Claim 21

In a data processing system which includes: a microprocessor apparatus operable in instruction cycles between a running state wherein instructions are processed and a wait state wherein no instructions are processed by the microprocessor and wherein microprocessor instructions generate enable and disable interrupt commands, the microprocessor generating instructions for changing page information, performing storage operations, branch and link operations and return operations; a page storage unit for storing page information which is set and reset to a zero state by microprocessor instructions; a storage unit for storing data and instructions; an arithmetic and logic unit having associated status bits which are set and reset to a zero state by microprocessor instructions; a plurality of peripheral devices connected to the microprocessor, the plurality of peripheral devices generating interrupt requests to the microprocessor for operating in an interrupt cycle; and the system operating in a pre-fetch mode wherein a next succeeding instruction is fetched from the storage unit while a current instruction is being executed, an interrupt system for processing interrupt requests received by the microprocessor from the plurality of peripheral devices comprising: instruction address register means coupled to the storage unit for holding the next succeeding address to be pre-fetched in a sequence of instructions and operable to be updated to the value of the next succeeding address; storage address register means coupled to said instruction address register means and coupled to the storage unit for holding the next succeeding instruction address during execution of the current instruction; first latch means coupled to the microprocessor for receiving and storing an interrupt request received from the microprocessor and generated by one of the plurality of peripheral devices; second latch means coupled to the storage unit and controlled by the microprocessor instructions for enabling and disabling interrupts that are received from the microprocessor when said first latch means has stored an interrupt request from the microprocessor; interrupt link register means coupled to said instruction address register means for storing the values stored in said instruction address register means when an interrupt request is generated from one of the plurality of peripheral devices to the microprocessor; interrupt means coupled to said first and second latch means for inhibiting the updating of the value of said instruction address register means to a next succeeding instruction to be pre-fetched during the first succeeding cycle following storage of an interrupt request by said first latch means; means coupled to said first and second latch means and responsive to a successful branch operation resulting from the next instruction stored in said instruction address register for inhibiting operation of said interrupt means until completion of said successful branch operation; means coupled to said first and second latch means and responsive to storage of data in the storage unit for inhibiting operation of said interrupt means until completion of the storage cycle; transfer means coupled to said instruction address register means and to said interrupt link register means for transferring the contents of said instruction address register means to said interrupt link register means upon the processing of an interrupt cycle by the microprocessor; restore means coupled to said intruction address register means and to said interrupt link register means for restoring the contents of said instruction address register means upon completion of execution of the interrupt cycle, such that said instruction address register means is available for use after the interrupt cycle has been completed by the microprocessor; means coupled to said interrupt means for recording each execution of each branch and link instruction and each return instruction generated by the microprocessor from the stroage unit while the microprocessor operates in the interrupt cycle; and means coupled to said interrupt means for determining the difference in the number of branch and link instructions and return instructions generated by the microprocessor, such that when the number of return instructions is greater than the number of branch and link instructions the interrupt cycle is completed and the return instruction causes the information stored in said interrupt link register means to be automatically restored from said interrupt link register means to said instruction address register.

Claim 22

The interrupt system of claim 18 wherein said interrupt means includes means for forcing an interrupt address from the storage unit to said storage address register means for accessing the next instruction from the storage unit for use in the next succeeding cycle of the microprocessor.

Claim 23

The interrupt system of claim 19 wherein said interrupt means includes means for storing in said interrupt link register the instruction address and page information stored in the page storage unit when the interrupt was executed by the microprocessor.

Claim 24

The interrupt system of claim 20 wherein said interrupt means includes means for storing in said interrupt link register the arithmetic and logic unit status bits stored in the arithmetic and logic unit when the interrupt was executed by the microprocessor.

Claim 25

The interrupt system of claim 20 wherein said interrupt means includes means for resetting of the contents of the page information stored in the page storage unit to a zero state.

Claim 26

The interrupt system of claim 20 wherein said interrupt means includes means for resetting of the contents of the arithmetic and logic unit status bits stored in the arithmetic and logic unit to a zero state.

Claim 27

The interrupt system of claim 20 wherein the microprocessor includes clock means and further includes: means for actuating the microprocessor clock means when an interrupt request occurs and the interrupt request has been enabled when the microprocessor is in the wait state.