US4097920A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware control for repeating program loops in electronic computers
Assignee: RCA Corp
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Filing: 1976-12-13
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Granted: 1978-06-27
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Expires: 1996-12-13
Abstract
Abstract Push-pop stack and counters added to automatic processor's program addressing and execution logic. A certain instruction, typically a load counter instruction, "pushes" the contents of the program counter (instruction address register) onto the stack (that is, loads the stack in the direction from top toward bottom). Other certain instructions, such as decrement and test counter, or special bits in all instructions decrement the last loaded counter's value by one and test for zero counter value. If the test is false, the instruction address register's contents are replaced by the top stack word and the program loop is repeated. The program loop is thus repeated until the test is true. When the test is true, the program counter addresses the next instruction in sequence and the stack is popped (its contents are shifted in the direction from the bottom toward the top of the stack), the top stack word being lost since the program loop will not be repeated. The counter pointer may be controlled by the program or may be automatic, i.e., under hardware control.
Inventors
- 👤 Stanley Edward Ozga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/325
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
173 words
In a system for executing loops of programmed instructions, said system including instruction addressing means for storing the memory address of a next instruction to be executed, instruction execution register means having an operation part and at least one address part for storing signals representing an instruction being executed, and control means including timing means for producing control signals in response to signals including signals from the operation part of said instruction execution register means, the improvement comprising: stack register means coupled to receive the contents of the instruction addressing means for storing addresses from said instruction addressing means in response to said control signals generated by certain non-branching instructions in said instruction execution register means, said stack register means including output means for providing signals representing the most recent instruction address stored; and gating means responsive to said control signals generated by other certain instructions in said instruction execution register means and to said stack register output means for gating signals from said stack register output means into said instruction addressing means.
Claim 2
Dependent Claim
173 words
In a system for executing loops of programmed instructions, said system including instruction addressing means for storing the memory address of a next instruction to be executed, instruction execution register means having an operation part and at least one address part for storing signals representing an instruction being executed, and control means including timing means for producing control signals in response to signals including signals from the operation part of said instruction execution register means, the improvement comprising: stack register means coupled to receive the contents of the instruction addressing means for storing addresses from said instruction addressing means in response to said control signals generated by certain non-branching instructions in said instruction execution register means, said stack register means including output means for providing signals representing the most recent instruction address stored; and gating means responsive to said control signals generated by other certain instructions in said instruction execution register means and to said stack register output means for gating signals from said stack register output means into said instruction addressing means.
Claim 3
Dependent Claim
117 words
The invention claimed in claim 1 further comprising: counter means for storing a value specified by said certain instructions; means for coupling said counter means to receive said address part of the instruction execution register means during the execution of said certain instructions; decrementing means responsive to control signals generated by said other certain instructions for decrementing the value stored in the counters; zero detect means responsive to said counter means value and to said other certain instructions for producing an output signal when the value stored in said counter has a value other than zero; and means coupling said zero detect means output signal to said control means for generating control signals to said gating means.
Claim 4
Dependent Claim
75 words
The invention as claimed in claim 2 wherein said stack register means comprises a push-pop stack means for storing a plurality of address words, said counter means comprises a plurality of counter means, each of said counter means associated with a particular one of said address words stored in said push-pop stack means, and said control means includes pointer means responsive to said certain instructions for providing control signals to said counter means in sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-26 | 1981-12-26 | 1982-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-26 | 1985-12-26 | 1986-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-26 | 1989-12-26 | 1990-06-27 | $7700.00 | Window Closed / Lapsed |