US3886523A
Expired / Lapsed
US
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Micro program data processor having parallel instruction flow streams for plural levels of sub instruction sets
Assignee: Unisys Corp
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Filing: 1973-10-02
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Granted: 1975-05-27
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Expires: 1993-10-02
Abstract
Abstract A micro program system is disclosed which employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control instructions that can be stored in a processor read-only memory. The respective micro instructions are made up of varying numbers of syllables according to the function of the particular micro instructions. The various types of micro instruction syllables are stored in a micro instruction memory to be fetched therefrom in sequence in accordance with the requirements of a particular macro instruction or subject instruction. In this manner, a variety of micro instructions can be created by selecting a plurality of different syllables from the micro instruction memory. A different micro instruction syllable is provided to specify each combination of the function to be performed and the source and destination registers to be used with the particular buses in the processor. In order to reduce the number of clock times required in the execution of the various micro instructions, micro instruction fetch and execution are overlapped and a micro instruction lookahead feature is provided. This results in there being two rather continuous and parallel instruction flow streams: one for the micro instructions being fetched from micro program store, and one for the control instructions being fetched from the control store.
Inventors
- 👤 Alisdair Cullen Ferguson
- 👤 John Mcgregor
- 👤 Alastair George Macpherson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28; G06F9/223
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
195 words
A data processing system having a micro instruction syllable memory portion and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received from said registers; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; micro instruction fetch means coupled to said micro instruction memory portion to fetch a sequence of micro instruction syllables; control instruction fetch means coupled to said control memory to fetch individual control instructions in response to respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause a sequence of micro instruction syllables to be fetched from said micro instruction memory and a corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of a particular control instruction for a preceding micro instruction syllable occurs concurrently with the fetch of the next micro instruction syllable in the sequence of micro instruction syllables.
Claim 2
Dependent Claim
195 words
A data processing system having a micro instruction syllable memory portion and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received from said registers; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; micro instruction fetch means coupled to said micro instruction memory portion to fetch a sequence of micro instruction syllables; control instruction fetch means coupled to said control memory to fetch individual control instructions in response to respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause a sequence of micro instruction syllables to be fetched from said micro instruction memory and a corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of a particular control instruction for a preceding micro instruction syllable occurs concurrently with the fetch of the next micro instruction syllable in the sequence of micro instruction syllables.
Claim 3
Dependent Claim
39 words
A system according to claim 1 including: circuit means coupling said control memory to said micro instruction memory fetch means to cause the fetch of an individual micro instruction syllable under control of one of said fetched control instructions.
Claim 4
Dependent Claim
67 words
A system according to claim 1 which includes a data memory portion and wherein the processor further includes: data segment fetch means coupled to said control memory and to said data memory portion to fetch data segments from said data memory portion, the fetch of a sequence of such data segments being under the control of a single fetched control instruction called for by micro instruction syllable.
Claim 5
Dependent Claim
40 words
A system according to claim 3 wherein the processor further includes: condition sensing means coupled to said data segment fetch means to halt the fetch of a sequence of data segments in repsonse to the occurrence of a sensed condition.
Claim 6
Dependent Claim
65 words
A system according to claim 1 wherein the processor includes: micro instruction receiving means coupled to said micro instruction memory portion to receive a micro instruction syllable fetched from said micro instruction memory portion, said micro instruction receiving means including means to determine the number of clock times required for execution prior to the fetch of a corresponding control instruction from said control instruction memory.
Claim 7
Dependent Claim
91 words
A system according to claim 5 wherein said timing means includes machine state means, said system further including: circuit means coupling said machine state means to said micro instruction syllable receiving means, said machine state means being responsive to the number of clock times required for execution of a micro instruction syllable to change the machine state of the machine state means, said machine state means having various states including a state of suspension during which additional micro instruction syllables are required to be fetched from said micro instruction memory portion.
Claim 8
Dependent Claim
83 words
A system according to claim 3 wherein said timing means includes machine sate means, said system further including: circuit means coupling said machine state means to said data segment receiving means, said machine state means being responsive to change its state according to the number of clock times required to execute the micro instruction syllables received, said machine state means having various states including the state of suspension during which additional data segments are required to be fetched from said data memory portion.
Claim 9
Dependent Claim
270 words
A data processing system having a macro instruction memory portion, a micro instruction memory portion, and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received from said general purpose registers; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; micro instruction fetch means coupled to said micro instruction memory portion to fetch a sequence of micro instruction syllables, said micro instruction fetch means including means to access said micro instruction memory portion and means to receive a syllable from said micro instruction memory portion; control instruction fetch means coupled to said control memory to fetch individual control instructions in rsponse to the respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause the sequence of micro instruction syllables to be fetched from said micro instruction memory portion and the corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of a particular control instruction for a previous micro instruction syllable occurs concurrently with the fetch of the next micro instruction syllable in the sequence of micro instruction syllables; said timing means being coupled to both said micro instruction memory access means and to said micro instruction syllable receiving means so as to effect the accessing of the next succeeding micro instruction syllable concurrently with the preceding micro instruction syllable.
Claim 10
Dependent Claim
270 words
A data processing system having a macro instruction memory portion, a micro instruction memory portion, and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received from said general purpose registers; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; micro instruction fetch means coupled to said micro instruction memory portion to fetch a sequence of micro instruction syllables, said micro instruction fetch means including means to access said micro instruction memory portion and means to receive a syllable from said micro instruction memory portion; control instruction fetch means coupled to said control memory to fetch individual control instructions in rsponse to the respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause the sequence of micro instruction syllables to be fetched from said micro instruction memory portion and the corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of a particular control instruction for a previous micro instruction syllable occurs concurrently with the fetch of the next micro instruction syllable in the sequence of micro instruction syllables; said timing means being coupled to both said micro instruction memory access means and to said micro instruction syllable receiving means so as to effect the accessing of the next succeeding micro instruction syllable concurrently with the preceding micro instruction syllable.
Claim 11
Dependent Claim
68 words
A system according to claim 8 which further includes: an address register to store addresses of said micro instruction syllable memory portion; and an incrementor means coupled to said address register; said timing means being coupled to said address register and said incrementor means to increment the contents of said address register concurrently with the access of a preceding micro instruction syllable in said micro instruction memory portion.
Claim 12
Dependent Claim
162 words
In a data processing system having a macro instruction memory portion, a micro instruction syllable memory portion, and a processor including a plurality of general purpose registers to temporarily store data, a function unit coupled to said general purpose registers to perform logical operations on data received therefrom and a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit in response to respective micro instruction syllables; the method of fetching Micro instruction syllables from said micro instruction memory and control instructions from said control instruction memory, said method comprising: fetching a sequence of micro instruction syllables from said micro instruction memory, one at a time; and fetching a corresponding sequence of control instructions from said control instruction memory, where the fetch of a control instruction associated with a preceding micro instruction syllable is performed concurrently with the fetch of the next succeeding micro instruction.
Claim 13
Dependent Claim
162 words
In a data processing system having a macro instruction memory portion, a micro instruction syllable memory portion, and a processor including a plurality of general purpose registers to temporarily store data, a function unit coupled to said general purpose registers to perform logical operations on data received therefrom and a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit in response to respective micro instruction syllables; the method of fetching Micro instruction syllables from said micro instruction memory and control instructions from said control instruction memory, said method comprising: fetching a sequence of micro instruction syllables from said micro instruction memory, one at a time; and fetching a corresponding sequence of control instructions from said control instruction memory, where the fetch of a control instruction associated with a preceding micro instruction syllable is performed concurrently with the fetch of the next succeeding micro instruction.
Claim 14
Dependent Claim
37 words
A method according to claim 10 including the step of: fetching a sequence of data segments from said micro instruction memory portion under the control of a single control instruction called for by a micro instruction syllable.
Claim 15
Dependent Claim
35 words
A method according to claim 11 including: sensing a condition; and halting the fetch of a sequence of data segments under control of a control instruction in response to the occurrence of a sensed condition.
Claim 16
Dependent Claim
44 words
A method according to claim 10 including: receiving a micro instruction syllable fetched from said micro instruction memory portion; and determining the number of clock times required for its execution prior to the fetch of a corresponding control instruction from the control instruction memory.
Claim 17
Dependent Claim
87 words
A method according to claim 13 wherein said processor includes machine state means having various machine states including a state of suspension during which additional micro instruction syllables are required to be fetched from said micro instruction memory portion, said method further including: changing the machine state of said machine state means and the processor in response to determination of the number of clock times required for an execution of a micro instruction prior to the fetch of a corresponding control instruction from said control instruction memory.
Claim 18
Dependent Claim
239 words
A data processing system having a macro instruction memory, a micro instruction syllable memory, and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received therefrom; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; macro instruction fetch means coupled to said macro instruction memory to fetch macro instruction operators therefrom; micro instruction fetch means coupled to said macro instruction fetch means and to said micro instruction memory to fetch a sequence of two or more micro instruction syllables from said micro instruction memory portion so as to perform a micro instruction called for by macro instruction operators; control instruction fetch means coupled to said control memory to fetch individual control instructions in response to respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause a sequence of micro instruction syllables to be fetched from said micro instruction memory and the corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of the particular control instruction for the preceding micro instruction syllable occurs concurrently with fetch of the next micro instruction syllable in the sequence of micro instruction syllables.
Claim 19
Dependent Claim
239 words
A data processing system having a macro instruction memory, a micro instruction syllable memory, and a processor, said processor comprising: a plurality of general purpose registers to temporarily store data; a function unit coupled to said general purpose registers to perform logical operations on data received therefrom; a control memory coupled to said registers and said function unit and containing control instructions to control data transfers between said general purpose registers and said function unit; macro instruction fetch means coupled to said macro instruction memory to fetch macro instruction operators therefrom; micro instruction fetch means coupled to said macro instruction fetch means and to said micro instruction memory to fetch a sequence of two or more micro instruction syllables from said micro instruction memory portion so as to perform a micro instruction called for by macro instruction operators; control instruction fetch means coupled to said control memory to fetch individual control instructions in response to respective micro instruction syllables; and timing means coupled to said micro instruction syllable fetch means and to said control instruction fetch means to cause a sequence of micro instruction syllables to be fetched from said micro instruction memory and the corresponding sequence of control instructions to be fetched from said control instruction memory where the fetch of the particular control instruction for the preceding micro instruction syllable occurs concurrently with fetch of the next micro instruction syllable in the sequence of micro instruction syllables.
Claim 20
Dependent Claim
39 words
A system according to claim 15 including: circuit means coupling said control memory to said micro instruction memory fetch means to cause the fetch of an individual micro instruction syllable under control of one of said fetched control instructions.
Claim 21
Dependent Claim
51 words
A system according to claim 15 wherein the processor further includes: data segment fetch means to fetch data segments from said macro instruction memory portion, the fetch of a Sequence of such data segments being under the control of a single fetched control instruction called for by a micro instruction syllable.
Claim 22
Dependent Claim
40 words
A system according to claim 17 wherein the processor further includes: condition sensing means coupled to said data segment fetch means to halt the fetch of a sequence of data segments in response to the occurrence of a sensed condition.
Claim 23
Dependent Claim
57 words
A system according to claim 15 wherein the processor includes: micro instruction receiving means to receive a micro instruction syllable fetched from said micro instruction memory, said micro instruction receiving means including means to determine the number of clock times required for execution prior to the fetch of a corresponding control instruction from the control instruction memory.
Claim 24
Dependent Claim
90 words
A system according to claim 19 wherein said timing means includes machine state means, said system further including: circuit means coupling said machine state means to said micro instruction syllable receiving means, said machine state means being responsive to the number of clock times required for execution of a micro instruction syllable to change the machine state of the machine state means, said machine state means having various states including a state of suspension during which additional micro instruction syllables are required to be fetched from said micro instruction memory.
Claim 25
Dependent Claim
82 words
A system according to claim 17 wherein said timing means includes machine state means, said system further including: circuit means coupling said machine state means to said data segment fetch means, said machine state means being responsive to change its state according to the number of clock times required to execute a micro instruction syllable, said machine state having various states including a state of suspension during which additional data segments are required to be fetched from said macro instruction memory portion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |