US6049487A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Embedded static random access memory for field programmable gate array
Assignee: Microsemi SoC Corp
•
Filing: 1998-03-16
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Granted: 2000-04-11
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Expires: 2018-03-16
Abstract
Abstract A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.
Inventors
- 👤 William C. Plants
- 👤 James Dean Joseph
- 👤 Antony G. Bell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G11C8/00; G11C8/16; G06; G06F; G06F11/00; G06F11/22; G06F11/2289
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
147 words
A dual ported static random access memory block comprising: a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs; a read port having a plurality of read address inputs, a plurality of read data inputs, a plurality of read enable inputs, a plurality of read output enable control inputs, and a read output enable input; and a write enable circuit in said write port connected to said plurality of write enable inputs, said write enable circuit having a plurality of polarity select circuits, each of said polarity select circuits having an input connected to one of said write enable inputs and an output, and an AND gate having a plurality of inputs and an output, each of said plurality of inputs connected to a separate one of said outputs of said polarity select circuits.
Claim 2
Dependent Claim
147 words
A dual ported static random access memory block comprising: a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs; a read port having a plurality of read address inputs, a plurality of read data inputs, a plurality of read enable inputs, a plurality of read output enable control inputs, and a read output enable input; and a write enable circuit in said write port connected to said plurality of write enable inputs, said write enable circuit having a plurality of polarity select circuits, each of said polarity select circuits having an input connected to one of said write enable inputs and an output, and an AND gate having a plurality of inputs and an output, each of said plurality of inputs connected to a separate one of said outputs of said polarity select circuits.
Claim 3
Dependent Claim
170 words
A dual ported static random access memory block comprising: a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs; a read port having a plurality of read address inputs, a plurality of read data inputs, a plurality of read enable inputs, a plurality of read output enable control inputs, and a read output enable input; and a read enable circuit in said read port connected to said plurality of read enable inputs, said read enable circuit having a plurality of select polarity circuits, each of said polarity select circuits having an input connected to one of said read enable inputs and an output, and an AND gate having a plurality of inputs and an output, each of said plurality of inputs connected to a separate one of said outputs of said polarity of select circuits, said out of said AND gate connected to an enable input of a latched sense amplifier connected to said read data outputs.
Claim 4
Dependent Claim
170 words
A dual ported static random access memory block comprising: a write port having a plurality of write address inputs, a plurality of write data inputs, and a plurality of write enable inputs; a read port having a plurality of read address inputs, a plurality of read data inputs, a plurality of read enable inputs, a plurality of read output enable control inputs, and a read output enable input; and a read enable circuit in said read port connected to said plurality of read enable inputs, said read enable circuit having a plurality of select polarity circuits, each of said polarity select circuits having an input connected to one of said read enable inputs and an output, and an AND gate having a plurality of inputs and an output, each of said plurality of inputs connected to a separate one of said outputs of said polarity of select circuits, said out of said AND gate connected to an enable input of a latched sense amplifier connected to said read data outputs.
Claim 5
Dependent Claim
201 words
A dual ported static random access memory as in claim 2 further including a read output enable circuit in said read port connected to said plurality of read output enable inputs and said read output enable control input, said read output enable circuit having a second plurality of polarity select circuits, a first one of said second plurality of polarity select circuits having an input connected to the said read output enable control input and an output, each of said second polarity select circuits having an input connected to one of said write output enable inputs and an output, an OR gate having a first input connected to said output of said AND gate, and a second input connected to said output of said first polarity select circuit and an output, and a second AND gate having a plurality of inputs and an output, a first one of said plurality of inputs connected to said output of said OR gate, and remaining ones of said plurality of said inputs connected to a separate one of said outputs of said second plurality of polarity select circuits, and an output connected to said enable circuit said enable input of said latched sense amplifier.
References Cited (Backward Citations)
US5869981A
Cited
US4930097A
Cited
EP0415542A2
Cited
US5198705A
Cited
US5222066A
Cited
US5880512A
Cited
US5187392A
Cited
US5883850A
Cited
US5848005A
Cited
US5208491A
Cited
US5744979A
Cited
US5831448A
Cited
US5861761A
Cited
US5809281A
Cited
US5375089A
Cited
US5365485A
Cited
US5815003A
Cited
US5859542A
Cited
US5838584A
Cited
US5847577A
Cited
US5850564A
Cited
US5850151A
Cited
US5850152A
Cited
US5838167A
Cited
US5838954A
Cited
US5825662A
Cited
US5880492A
Cited
US5815004A
Cited
US5870586A
Cited
US5744980A
Cited
US5801547A
Cited
US5835998A
Cited
US5847441A
Cited
US5852608A
Cited
US5825201A
Cited
US5828538A
Cited
US5859543A
Cited
US5825200A
Cited
US5859544A
Cited
US5880597A
Cited
US5825202A
Cited
US5828230A
Cited
US5880598A
Cited
US5821776A
Cited
US5883526A
Cited
EP0899591A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |