US5825202A
Expired / Lapsed
US
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Integrated circuit with field programmable and application specific logic areas
Assignee: Xilinx Inc
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Filing: 1996-09-26
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Granted: 1998-10-20
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Expires: 2016-09-26
Abstract
Abstract A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.
Inventors
- 👤 Danesh Tavana
- 👤 Wilson K. Yee
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/1778; H03K19/17796
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
94 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnect ions comprising arrays of programmable and mask-defined interconnections.
Claim 2
Dependent Claim
94 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnect ions comprising arrays of programmable and mask-defined interconnections.
Claim 3
Dependent Claim
66 words
The integrated circuit recited in claim 1 wherein said plurality of first interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectable intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.
Claim 4
Dependent Claim
29 words
The integrated circuit recited in claim 1 further comprising a plurality of second interconnections between said array of programmable gates and a portion of said plurality of input/output pads.
Claim 5
Dependent Claim
66 words
The integrated circuit recited in claim 3 wherein said plurality of second interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectably intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.
Claim 6
Dependent Claim
29 words
The integrated circuit recited in claim 1 further comprising a plurality of third interconnections between said array of mask-defined gates and a portion of said plurality of input/output pads.
Claim 7
Dependent Claim
66 words
The integrated circuit recited in claim 5 wherein said plurality of third interconnections comprises a first matrix of field programmable interconnections and a second matrix of mask-defined permanent interconnections, said first matrix and said second matrix each having a plurality of selectably intersecting rows and columns of electrically conductive paths, the respective rows of said first matrix being connected to corresponding rows of said second matrix.
Claim 8
Dependent Claim
28 words
The integrated circuit recited in claim 1 further comprising a plurality of clock pads providing externally accessible clock connections to said arrays of programmable gates and mask-defined gates.
Claim 9
Dependent Claim
23 words
The integrated circuit recited in claim 7 wherein at least one of said clock pads is programmably connectable to both of said arrays.
Claim 10
Dependent Claim
49 words
The integrated circuit recited in claim 1 wherein said plurality of first interconnections between said arrays of programmable gates and said mask-defined gates comprises a plurality of long lines extending past more than one of said field programmable gates and connected to at least one of said switch matrices.
Claim 11
Dependent Claim
28 words
The integrated circuit of claim 1 wherein said plurality of first interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.
Claim 12
Dependent Claim
28 words
The integrated circuit of claim 3 wherein said plurality of second interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.
Claim 13
Dependent Claim
28 words
The integrated circuit of claim 5 wherein said plurality of third interconnections occupy integrated-circuit resources substantially separate from integrated-circuit resources occupied by said array of field programmable gates.
Claim 14
Dependent Claim
91 words
An integrated circuit chip comprising: a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections; a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising arrays of field-configured and mask-defined interconnections.
Claim 15
Dependent Claim
91 words
An integrated circuit chip comprising: a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections; a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising arrays of field-configured and mask-defined interconnections.
Claim 16
Dependent Claim
21 words
The integrated circuit chip recited in claim 13 wherein each of said arrays occupies a respective distinct portion of said chip.
Claim 17
Dependent Claim
37 words
The integrated circuit chip recited in claim 13 wherein said interconnect structure comprises signal routing having a plurality of selectable interconnections, some of said interconnections being mask-defined and some of said interconnections being field selectable by programming.
Claim 18
Dependent Claim
24 words
The integrated circuit chip recited in claim 15 wherein said mask-defined interconnections and said field selectable interconnections comprise matrices configured as columns and rows.
Claim 19
Dependent Claim
110 words
An integrated circuit configured as a monolithic chip and comprising: a plurality of logic blocks the logic functions of which may be configured after packaging of said chip, said blocks being interconnected by configurable interconnects in the form of paths which may also be configured after packaging of said chip; and an array of mask-defined logic gates the logic functions of which are selected before packaging of said chip, said gates being interconnected by paths selected before packaging of said chip, said paths comprising an interconnect-element array; said logic blocks and said gates being interconnected by paths at least some of which may be configured after packaging of said chip.
Claim 20
Dependent Claim
110 words
An integrated circuit configured as a monolithic chip and comprising: a plurality of logic blocks the logic functions of which may be configured after packaging of said chip, said blocks being interconnected by configurable interconnects in the form of paths which may also be configured after packaging of said chip; and an array of mask-defined logic gates the logic functions of which are selected before packaging of said chip, said gates being interconnected by paths selected before packaging of said chip, said paths comprising an interconnect-element array; said logic blocks and said gates being interconnected by paths at least some of which may be configured after packaging of said chip.
Claim 21
Independent Claim
88 words
A method of fabricating an integrated circuit with field programmable and application specific logic areas, the method comprising the following steps: a) providing an array of mask defined logic gates; b) providing an array of field programmable logic gates; c) programming unalterable logic functions of said mask defined logic gates; d) providing a structure for programming alterable logic functions of said field programmable logic gates; and e) providing and programming arrays of field-configured and mask-defined interconnections between said mask defined logic gates and said field programmable logic gates.
Claim 22
Independent Claim
88 words
A method of fabricating an integrated circuit with field programmable and application specific logic areas, the method comprising the following steps: a) providing an array of mask defined logic gates; b) providing an array of field programmable logic gates; c) programming unalterable logic functions of said mask defined logic gates; d) providing a structure for programming alterable logic functions of said field programmable logic gates; and e) providing and programming arrays of field-configured and mask-defined interconnections between said mask defined logic gates and said field programmable logic gates.
Claim 23
Dependent Claim
103 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnections comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.
Claim 24
Dependent Claim
103 words
A monolithic integrated circuit comprising: an array of field programmable gates selectively interconnected by programmable switch matrices, said gates and said switch matrices being selectively programmable after manufacture in accordance with desired gate functions and connection relationships; an array of mask-defined gates having permanent customized functions and connection relationships; a plurality of input/output pads providing externally accessible signal connections to said arrays of programmable gates and mask-defined gates; and a plurality of first interconnections between said arrays of programmable gates and mask-defined gates, said first interconnections comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.
Claim 25
Dependent Claim
101 words
An integrated circuit chip comprising: a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections; a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.
Claim 26
Dependent Claim
101 words
An integrated circuit chip comprising: a field-configured array of logic blocks having logic functions and being interconnected in accordance with user provided data which may be modified to alter the field-configured array of logic blocks to have different respective logic functions and interconnections; a mask-defined array of logic blocks having respective logic functions and being interconnected in accordance with selected metal masks which, once selected, cannot be modified; and an interconnect structure for connecting said field-configured array to said mask-defined array, said interconnect structure comprising programmable interconnections dedicated to the function of interconnecting the field programmable gates to the mask-defined gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |