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US5687325A Expired / Lapsed US ⏱️ 0.0 years remaining

Application specific field programmable gate array

Assignee: Intellectual Ventures II LLC
•
Filing: 1996-04-19
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Granted: 1997-11-11
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Expires: 2016-04-19
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Abstract

Abstract An application specific field programmable gate array ("ASFPGA") includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed functional units may include one or more bus interfaces, event timers, an interrupt controller, a Direct Memory Access ("DMA") controller, system timers, a real-time clock, a Random Access Memory ("RAM"), a clock synthesizer, a RAM Digital-to-Analog Converter ("DAC"), a display interface, a register file, a compressed image encoder/decoder ("CODEC"), or similar functional units. The ASFPGA also includes a general purpose field programmable gate array ("FPGA"). The FPGA is configurable to effect a specific digital logic circuit interconnection between fixed functional units. After the FPGA has been configured, the fixed functional units together with the FPGA perform all the functions specified for a particular ASIC design.

Inventors

  • 👤 Web Chang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 23:19
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F30/00; G06F30/30; G06F30/34; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 61 words
An application specific field programmable gate array ("ASFPGA") comprising: at least two fixed functional units included in a single integrated circuit ("IC") chip; and a general purpose field programmable gate array ("FPGA") also included in the IC chip, said FPGA interconnecting the fixed functional units, and being programmable to effect a specific digital logic circuit interconnection of the fixed functional units.
Claim 2
Dependent Claim 61 words
An application specific field programmable gate array ("ASFPGA") comprising: at least two fixed functional units included in a single integrated circuit ("IC") chip; and a general purpose field programmable gate array ("FPGA") also included in the IC chip, said FPGA interconnecting the fixed functional units, and being programmable to effect a specific digital logic circuit interconnection of the fixed functional units.
Claim 3
Dependent Claim 18 words
The ASFPGA of claim 1 wherein at least one of the fixed functional units is a bus interface.
Claim 4
Dependent Claim 17 words
The ASFPGA of claim 2 wherein the bus interface is an industry standard architecture ("ISA") bus interface.
Claim 5
Dependent Claim 17 words
The ASFPGA of claim 2 wherein the bus interface is an Peripheral Component Interconnect ("PCI") bus interface.
Claim 6
Dependent Claim 13 words
The ASFPGA of claim 4 wherein the ASFPGA includes a second bus interface.
Claim 7
Dependent Claim 15 words
The ASFPGA of claim 5 wherein the second bus interface is an ISA bus interface.
Claim 8
Dependent Claim 14 words
The ASFPGA of claim 1 wherein the ASFPGA is a System Logic Controller ("SLC").
Claim 9
Dependent Claim 31 words
The ASFPGA of claim 7 wherein the SLC includes interrupt controller fixed functional unit and a Direct Memory Access ("DMA") controller fixed functional unit that are all coupled to said FPGA.
Claim 10
Dependent Claim 12 words
The ASFPGA of claim 1 wherein the ASFPGA is a graphic controller.
Claim 11
Dependent Claim 34 words
The ASFPGA of claim 9 wherein the graphic controller includes Random Access Memory ("RAM") Digital-to-Analog Converter ("DAC") fixed functional unit and a display interface fixed functional unit that are all coupled to said FPGA.
Claim 12
Dependent Claim 12 words
The ASFPGA of claim 10 wherein the ASFPGA is a switching hub.
Claim 13
Dependent Claim 39 words
The ASFPGA of claim 11 wherein the switching hub is includes a switching-hub port fixed functional unit, a bus arbiter fixed functional unit; and a content addressed memory ("CAM") fixed functional unit that are all coupled to said FPGA.

References Cited (Backward Citations)

US5361373A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-11-10 2001-05-12 2001-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-11-10 2005-05-12 2005-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-11-10 2009-05-12 2009-11-11 $7700.00 Window Closed / Lapsed

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