US4930097A
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Architecture for an improved performance of a programmable logic device
Assignee: Altera Corp
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Filing: 1988-12-30
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Granted: 1990-05-29
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Expires: 2008-12-30
Abstract
Abstract A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and non-inverting buffer, wherein the memory cells are coupled to enable the buffers. The stored state of each of the memory cells determines if a corresponding buffer is to be activated. In one embodiment, a memory cell is provided for each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the outputs of each pair of complementary buffers are inputted to a multiplexer, wherein a corresponding memory cell coupled to its multiplexer controls the selection of the signal or its complement to be outputted.
Inventors
- 👤 Gregory W. Ledenbach
- 👤 Michael J. Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
125 words
In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, an apparatus for operating on said inputs according to a stored program, comprising: a plurality of memory cells for storing said program; a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output; for each said buffer, a corresponding one of said memory cells is coupled to enable said buffer for passing said input signal as said corresponding output, wherein enablement of each said buffer is determined by a stored state of its corresponding memory cell and wherein said corresponding output from each said buffer provides for said plurality of outputs from said PLD.
Claim 2
Dependent Claim
125 words
In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, an apparatus for operating on said inputs according to a stored program, comprising: a plurality of memory cells for storing said program; a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output; for each said buffer, a corresponding one of said memory cells is coupled to enable said buffer for passing said input signal as said corresponding output, wherein enablement of each said buffer is determined by a stored state of its corresponding memory cell and wherein said corresponding output from each said buffer provides for said plurality of outputs from said PLD.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1 wherein each said buffer is comprised of an inverter and a non-inverter such that one of said inverter and non-inverter is enabled by its buffer's corresponding memory cell.
Claim 4
Dependent Claim
24 words
The apparatus of claim 2 wherein outputs from each pair of said inverter and non-inverter are coupled together as inputs to an AND gate.
Claim 5
Dependent Claim
17 words
The apparatus of claim 3 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
Claim 6
Dependent Claim
47 words
The apparatus of claim 4 wherein said memory cells are arranged in an array and selective pairs of inverter and non-inverter outputs are coupled to one of a plurality of AND gates and an output from each AND gate provides for a product term for said PLD.
Claim 7
Dependent Claim
115 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs if enabled, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; for each said buffer, a corresponding one of said memory cells is coupled to enable its buffer for passing said input signal or its complement, wherein enablement of each said buffer is determined by a stored state of said corresponding memory cell.
Claim 8
Dependent Claim
115 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs, wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs if enabled, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; for each said buffer, a corresponding one of said memory cells is coupled to enable its buffer for passing said input signal or its complement, wherein enablement of each said buffer is determined by a stored state of said corresponding memory cell.
Claim 9
Dependent Claim
16 words
The PLD of claim 6 wherein each said buffer also provides level translation of said input.
Claim 10
Dependent Claim
35 words
The PLD of claim 7 wherein outputs from each pair of said inverter and non-inverter are coupled together to provide an input to an AND logic means to determine a product term from said array.
Claim 11
Dependent Claim
17 words
The PLD of claim 8 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
Claim 12
Dependent Claim
21 words
The PLD of claim 9 wherein said buffers are distributed within said array and disposed proximate to said corresponding memory cell.
Claim 13
Dependent Claim
122 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells for storing said program; a plurality of buffers wherein each of said inputs is coupled to at least one of said buffers; a plurality of multiplexers (MUXs) each coupled to a corresponding buffer for receiving an output from its corresponding buffer as its input; for each said MUX, a corresponding one of said memory cells is coupled to enable said MUX for passing its input signal as an output from said MUX, wherein enablement of said MUX is determined by a stored state of said corresponding memory cell.
Claim 14
Dependent Claim
122 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells for storing said program; a plurality of buffers wherein each of said inputs is coupled to at least one of said buffers; a plurality of multiplexers (MUXs) each coupled to a corresponding buffer for receiving an output from its corresponding buffer as its input; for each said MUX, a corresponding one of said memory cells is coupled to enable said MUX for passing its input signal as an output from said MUX, wherein enablement of said MUX is determined by a stored state of said corresponding memory cell.
Claim 15
Dependent Claim
53 words
The PLD of claim 11 wherein said buffer for each said input is comprised of an inverter and a non-inverter and outputs of said inverter and non-inverter are coupled as a complement pair of inputs to its MUX and said corresponding memory cell for its MUX selects between said complement pair of inputs.
Claim 16
Dependent Claim
30 words
The PLD of claim 12 wherein outputs from said MUXs are coupled together to provide an input to an AND logic means to determine a product term from said PLD.
Claim 17
Dependent Claim
17 words
The PLD of claim 13 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
Claim 18
Dependent Claim
129 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive its input and its complement; for each said MUX, a corresponding one of said memory cells is coupled to select between its corresponding input or its complement, wherein selection of said MUX is determined by a stored state of said corresponding memory cell.
Claim 19
Dependent Claim
129 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs wherein said outputs are determined by a stored program operating on said inputs, comprising: a plurality of memory cells arranged in an array for storing said program; a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive its input and its complement; for each said MUX, a corresponding one of said memory cells is coupled to select between its corresponding input or its complement, wherein selection of said MUX is determined by a stored state of said corresponding memory cell.
Claim 20
Dependent Claim
16 words
The PLD of claim 15 wherein each said buffer also provides level translation of said input.
Claim 21
Dependent Claim
30 words
The PLD of claim 16 wherein outputs from said MUS are coupled together to provide an input to an AND logic means to determine a product term from said PLD.
Claim 22
Dependent Claim
17 words
The PLD of claim 16 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |