Multi-buffered configurable logic block output lines in a field programmable gate array

Claim 2

An output driver configuration for a logic block comprising: a first buffer coupled to an output port of the logic block for driving an output signal; a second buffer coupled to the output port of the logic block for driving the output signal; a first output line coupled to the first buffer; means for programmably coupling the first output line to one of a critical interconnect path and a non-critical interconnect path for the output signal; a second output line coupled to the second buffer; and means for programmably coupling the second output line to one of a critical interconnect path and a non-critical interconnect path for the output signal.

Claim 3

The output driver configuration of claim 1, wherein the means for programmably coupling the first output line includes: a third line; and a programmable interconnect point coupled to the third line and the first output line, wherein the programmable interconnect point selectively provides the output signal from the first output line to at least the third line.

Claim 4

The output driver configuration of claim 1, wherein the means for programmably coupling the second output line includes: a third line; and a programmable interconnect point coupled to the third line and the second output line, wherein the programmable interconnect point selectively provides the output signal from the second output line to at least the third line.

Claim 5

The output driver configuration of claim 1, wherein the means for programmably coupling includes a switch matrix coupled to a plurality of interconnect lines, wherein the switch matrix programmably routes the output signal to one or more of the plurality of interconnect lines.

Claim 6

The output driver configuration of claim 1, wherein the first output line and the second output line are single-length lines.

Claim 7

The output driver configuration of claim 1, wherein the first output line and the second output line are double-length lines.

Claim 8

The output driver configuration of claim 1, wherein the first output line and the second output line are longlines.

Claim 9

The output driver configuration of claim 1, wherein the logic block is a configurable logic block.

Claim 10

The output driver configuration of claim 1, wherein the logic block is an input/output block.

Claim 11

A programmable logic device comprising: a logic block including an input port for receiving an input signal, means for processing the input signal, and an output port for providing an output signal; an interconnect structure for programmably interconnecting the logic block to other portions of the programmable logic device, the interconnect structure including: a plurality of horizontal interconnect lines; a plurality of vertical interconnect lines; and a plurality of switch matrices located at some of the intersections of the horizontal and vertical interconnect lines for programmable coupling certain horizontal and vertical interconnect lines, a first interconnect line programmably coupled to the output port, wherein the first interconnect line becomes part of one of a critical path and a non-critical path; a first buffer coupled between the output port and the first interconnect line for driving the output signal on the first interconnect line; a second interconnect line programmably coupled to the output port, wherein the second interconnect line becomes part of one of a critical path and a non-critical path; and a second buffer coupled between the output port and the second interconnect line for driving the output signal on the second interconnect line.

Claim 12

A programmable logic device comprising: a logic block including an input port for receiving an input signal, means for processing the input signal, and an output port for providing an output signal; an interconnect structure for programmably interconnecting the logic block to other portions of the programmable logic device, the interconnect structure including: a plurality of horizontal interconnect lines; a plurality of vertical interconnect lines; and a plurality of switch matrices located at some of the intersections of the horizontal and vertical interconnect lines for programmable coupling certain horizontal and vertical interconnect lines, a first interconnect line programmably coupled to the output port, wherein the first interconnect line becomes part of one of a critical path and a non-critical path; a first buffer coupled between the output port and the first interconnect line for driving the output signal on the first interconnect line; a second interconnect line programmably coupled to the output port, wherein the second interconnect line becomes part of one of a critical path and a non-critical path; and a second buffer coupled between the output port and the second interconnect line for driving the output signal on the second interconnect line.

Claim 13

The programmable logic device of claim 10, wherein the first interconnect line and the second interconnect line are single-length lines.

Claim 14

The programmable logic device of claim 10, wherein the first interconnect line and the second interconnect line are double-length lines.

Claim 15

The programmable logic device of claim 10, wherein the first interconnect line and the second interconnect line are longlines.

Claim 16

The programmable logic device of claim 10, wherein the logic block is a configurable logic block.

Claim 17

The programmable logic device of claim 10, wherein the logic block is an input/output block.

Claim 18

In a programmable logic chip, a method of isolating a critical path that conducts a logic block output signal from non-critical paths upon which the output signal is conducted, the method comprising the steps of: driving the output signal onto a first line by a first buffer; programmably routing the output signal from the first line onto a plurality of interconnect lines, wherein the first line forms part of the non-critical paths; driving the output signal onto a second line by a second buffer; and programmably routing the output signal from the second line onto an interconnect line, wherein the second line forms part of the critical path, and wherein the second buffer is not loaded with the first line and the plurality of interconnect lines.

Claim 19

In a programmable logic chip, a method of isolating a critical path that conducts a logic block output signal from non-critical paths upon which the output signal is conducted, the method comprising the steps of: driving the output signal onto a first line by a first buffer; programmably routing the output signal from the first line onto a plurality of interconnect lines, wherein the first line forms part of the non-critical paths; driving the output signal onto a second line by a second buffer; and programmably routing the output signal from the second line onto an interconnect line, wherein the second line forms part of the critical path, and wherein the second buffer is not loaded with the first line and the plurality of interconnect lines.

Claim 20

The method of claim 16, wherein an output port of the logic block is coupled to an input terminal of the first buffer and to an input terminal of the second buffer.

Claim 21

The method of claim 17, wherein the first line and the second line include single-length lines.

Claim 22

The method of claim 17, wherein the first line and the second line include double-length lines.

Claim 23

The method of claim 17, wherein the first line and the second line include longlines.

Claim 24

The output driver configuration of claim 1, wherein the first buffer includes a first inverter and a second inverter coupled in series, and wherein the second buffer includes the first inverter and a third inverter coupled in series.