US5600263A
Expired / Lapsed
US
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Configuration modes for a time multiplexed programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-08-18
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Granted: 1997-02-04
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Expires: 2015-08-18
Abstract
Abstract A PLD is operable in a variety of modes. In a first mode, the timeshare mode, the PLD remains at a single configuration for a plurality of user clock cycles. In a second mode, the logic engine mode, the PLD sequences through multiple configurations for each user cycle. In this mode, the period of time during which a configuration is active is called a micro cycle. In a third mode, the static mode, multiple configurations are programmed identically, so that the PLD performs the same function regardless of the configuration. Finally, the PLD is also operable in a combination mode, wherein part of the chip operates in one mode, for example, the static mode, and another part of the chip operates in the logic engine mode or the timeshare mode. In an alternative or co-existing embodiment, the PLD operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.
Inventors
- 👤 Stephen M. Trimberger
- 👤 Richard A. Carberry
- 👤 Robert A. Johnson
- 👤 Jennifer Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:17
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
50 words
A method of time multiplexing a programmable logic device comprising the steps of: providing at least one configurable element; providing a plurality of configuration memory points for configuring said at least one configurable element, wherein each of said configuration memory points includes a plurality of memory cells and a latch.
Claim 2
Independent Claim
50 words
A method of time multiplexing a programmable logic device comprising the steps of: providing at least one configurable element; providing a plurality of configuration memory points for configuring said at least one configurable element, wherein each of said configuration memory points includes a plurality of memory cells and a latch.
Claim 3
Dependent Claim
44 words
The method of claim 1 including providing a plurality of configuration modes for said programmable logic device, wherein said programmable logic device operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle.
Claim 4
Dependent Claim
43 words
The method of claim 1 including providing a plurality of configuration modes for said programmable logic device, wherein a portion of said configurable elements are configured in one configuration mode and another portion of said configurable elements are configured in another configuration mode.
Claim 5
Dependent Claim
82 words
The method of claim 1 including providing a plurality of configuration modes for said programmable logic device, wherein said programmable logic device operates in one configuration mode during at least one user cycle and in another configuration mode during at least another user cycle; and providing a plurality of configuration modes for said programmable logic device, wherein a portion of said configurable elements are configured in one configuration mode and another portion of said configurable elements are configured in another configuration mode.
Claim 6
Independent Claim
72 words
A method of time multiplexing a programmable logic device comprising the steps of: providing at least one configurable element including a plurality of configurable combinational logic elements and a plurality of configurable sequential logic elements; providing a plurality of configuration memory points for configuring said plurality of configurable combinational logic elements and said plurality of configurable sequential logic elements, wherein each of said configuration memory points includes a plurality of memory cells.
Claim 7
Independent Claim
72 words
A method of time multiplexing a programmable logic device comprising the steps of: providing at least one configurable element including a plurality of configurable combinational logic elements and a plurality of configurable sequential logic elements; providing a plurality of configuration memory points for configuring said plurality of configurable combinational logic elements and said plurality of configurable sequential logic elements, wherein each of said configuration memory points includes a plurality of memory cells.
Claim 8
Independent Claim
51 words
A method of time multiplexing a programmable logic device comprising a timeshare mode wherein said programmable logic device remains at a single configuration for a plurality of user clock cycles and saves and restores a state value, wherein said step of saving and restoring is done on said programmable logic device.
Claim 9
Independent Claim
51 words
A method of time multiplexing a programmable logic device comprising a timeshare mode wherein said programmable logic device remains at a single configuration for a plurality of user clock cycles and saves and restores a state value, wherein said step of saving and restoring is done on said programmable logic device.
Claim 10
Dependent Claim
15 words
The method of claim 6 wherein said saving and restoring is done after a configuration.
Claim 11
Independent Claim
35 words
A method of time multiplexing a programmable logic device comprising a timeshare mode wherein said programmable logic device remains at a single configuration for a plurality of user clock cycles and recirculates a state value.
Claim 12
Independent Claim
35 words
A method of time multiplexing a programmable logic device comprising a timeshare mode wherein said programmable logic device remains at a single configuration for a plurality of user clock cycles and recirculates a state value.
Claim 13
Independent Claim
31 words
A method of time multiplexing a programmable logic device comprising providing a logic engine mode wherein said programmable logic device sequences through three or more configurations in one user clock cycle.
Claim 14
Independent Claim
31 words
A method of time multiplexing a programmable logic device comprising providing a logic engine mode wherein said programmable logic device sequences through three or more configurations in one user clock cycle.
Claim 15
Dependent Claim
19 words
The method of claim 9 wherein the sequencing is triggered by a signal external to said programmable logic device.
Claim 16
Dependent Claim
25 words
The method of claim 9 wherein the sequencing is triggered by a signal generated by at least one configurable element in said programmable logic device.
Claim 17
Dependent Claim
21 words
The method of claim 9 wherein the sequencing of said plurality of configurations is repeated in a next user clock cycle.
Claim 18
Dependent Claim
31 words
The method of claim 9 further including providing a plurality of configuration modes for said programmable logic device, wherein at least one of said configuration modes includes said logic engine mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |