US5859542A
Expired / Lapsed
US
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Programmable logic array integrated circuits with enhanced cascade
Assignee: Altera Corp
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Filing: 1997-07-22
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Granted: 1999-01-12
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Expires: 2017-07-22
Abstract
Abstract A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABS) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).
Inventors
- 👤 Bruce B. Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
110 words
A configurable electronic device comprising: at least one logic element comprising at least one output and a plurality of inputs wherein at least one output can be configured to represent any combinatorial function of said inputs and wherein at least one logic element has associated with it: a cascade logic gate for combining an input directed to said configurable logic element with an output of another configurable logic element said output of another configurable logic element representing any combinatorial function of inputs of said another configurable logic element; and a cascade connector for conveying a signal from said output of said another configurable logic element to said cascade logic gate.
Claim 2
Dependent Claim
110 words
A configurable electronic device comprising: at least one logic element comprising at least one output and a plurality of inputs wherein at least one output can be configured to represent any combinatorial function of said inputs and wherein at least one logic element has associated with it: a cascade logic gate for combining an input directed to said configurable logic element with an output of another configurable logic element said output of another configurable logic element representing any combinatorial function of inputs of said another configurable logic element; and a cascade connector for conveying a signal from said output of said another configurable logic element to said cascade logic gate.
Claim 3
Dependent Claim
57 words
The configurable electronic device according to claim 1 wherein said logic element further has associated with it a cascade selector with its output coupled to an input of said cascade logic gate, one of its selectable inputs coupled to said cascade connector and another of its selectable inputs coupled to a signal providing a constant logic value.
Claim 4
Dependent Claim
31 words
The configurable electronic device as recited in claim 1 wherein the configurable electronic device is connected to a system, said system comprising: a processing unit; a memory; and an input/output interface.
Claim 5
Independent Claim
93 words
A method in a programmable logic device of logically combining configurable logic element signals, wherein said configurable logic element comprises an output that can represent any combinatorial function of inputs of said configurable logic element comprising the steps of: providing at least one configurable logic element with a cascade logic gate; and routing an output signal from another configurable logic element to an input of said cascade logic gate such that said output signal may be selectably combined with a signal directed to an input of said at least one configurable logic element.
Claim 6
Independent Claim
93 words
A method in a programmable logic device of logically combining configurable logic element signals, wherein said configurable logic element comprises an output that can represent any combinatorial function of inputs of said configurable logic element comprising the steps of: providing at least one configurable logic element with a cascade logic gate; and routing an output signal from another configurable logic element to an input of said cascade logic gate such that said output signal may be selectably combined with a signal directed to an input of said at least one configurable logic element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |