US5848005A
Expired / Lapsed
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Programmable logic array integrated circuits
Assignee: Altera Corp
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Filing: 1997-05-06
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Granted: 1998-12-08
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Expires: 2017-05-06
Abstract
Abstract A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
Inventors
- 👤 Richard G. Cliff
- 👤 L. Todd Cope
- 👤 Cameron R. McClintock
- 👤 William Leong
- 👤 James A. Watson
- 👤 Joseph Huang
- 👤 Bahram Ahanin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:15
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; G; G11; G11C; G11C8/00; G11C8/12; H03K19/173; H03K19/1733; H03K19/1737; H03K19/177; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1774; H03K19/17748; H03K19/1776; H03K19/1778; H03K19/17792; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
187 words
A programmable logic device organized in a two-dimensional array comprising: a first plurality of conductors, each of said first plurality of conductors provided in a first dimension of said two dimensional array; a second plurality of conductors, each of said second plurality of conductors provided in a second dimension of said two dimensional array; a plurality of logic blocks devoted substantially to logic functions, each of said logic blocks programmably coupled to at least one of said first or second plurality of conductors; and a plurality of memory blocks devoted substantially to user memory, each of said memory blocks programmably coupled to at least one of said first or second plurality of conductors, wherein a selected number of said plurality of logic blocks are configured to provide a plurality of registers and multiplexers, each of said registers configured to receive a first data input and a first clock input and each of said multiplexers configured to receive a second data input, said multiplexers coupled to at least one of said plurality of memory blocks, said at least one memory block configured to receive a second clock input.
Claim 2
Dependent Claim
187 words
A programmable logic device organized in a two-dimensional array comprising: a first plurality of conductors, each of said first plurality of conductors provided in a first dimension of said two dimensional array; a second plurality of conductors, each of said second plurality of conductors provided in a second dimension of said two dimensional array; a plurality of logic blocks devoted substantially to logic functions, each of said logic blocks programmably coupled to at least one of said first or second plurality of conductors; and a plurality of memory blocks devoted substantially to user memory, each of said memory blocks programmably coupled to at least one of said first or second plurality of conductors, wherein a selected number of said plurality of logic blocks are configured to provide a plurality of registers and multiplexers, each of said registers configured to receive a first data input and a first clock input and each of said multiplexers configured to receive a second data input, said multiplexers coupled to at least one of said plurality of memory blocks, said at least one memory block configured to receive a second clock input.
Claim 3
Dependent Claim
54 words
The programmable logic device of claim 1 wherein said multiplexers are configured to provide a selected memory block input to said at least one memory block from said first data input or said second data input, said selected memory block input stored in said at least one memory block by said second clock input.
Claim 4
Dependent Claim
32 words
The programmable logic device of claim 1 wherein said selected number of logic blocks are configured to provide an output register coupled to an output of said at least one memory block.
Claim 5
Dependent Claim
36 words
The programmable logic device of claim 1 wherein each of said memory blocks further comprises: a plurality of memory columns; and a control unit coupling said first plurality of conductors to said plurality of memory columns.
Claim 6
Dependent Claim
33 words
The programmable logic device of claim 4 wherein each of said memory blocks further comprises: a data input register coupled to said memory columns; and an address register coupled to said control unit.
Claim 7
Dependent Claim
24 words
The programmable logic device of claim 5 wherein each of said memory blocks further comprises a data output register coupled to said memory columns.
Claim 8
Dependent Claim
21 words
The programmable logic device of claim 6 wherein said data output register is programmably coupled to said second plurality of conductors.
Claim 9
Dependent Claim
53 words
The programmable logic device of claim 5 wherein said control unit further comprises: an address encoder coupled to said address register; an address control circuit having inputs coupled to said address encoder and to said plurality of first plurality of conductors; and an address decoder having inputs coupled to said address control circuit.
Claim 10
Dependent Claim
32 words
The programmable logic device of claim 5 wherein said control unit further comprises a read/write control circuit having a plurality of inputs and a plurality of outputs coupled to said memory columns.
Claim 11
Dependent Claim
35 words
The programmable logic device of claim 9 wherein said plurality of inputs to said read/write control circuit further comprise: a program mode signal from said address register; an address clock; and a write enable signal.
Claim 12
Dependent Claim
38 words
The programmable logic device of claim 6 wherein said control unit further comprises a clock/output enable generator having a plurality of inputs coupled to said first plurality of conductors and an output coupled to said data output register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |