Patent US6041014A successfully refreshed from Google Patents.
US6041014A
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Nonvolatile semiconductor memory device having row decoder
Assignee: STMicroelectronics SRL
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Filing: 1999-05-10
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Granted: 2000-03-21
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Expires: 2019-05-10
Abstract
Abstract A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.
Inventors
- 👤 Shigeru Atsumi
- 👤 Sumio Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:20
CPC Classifications
G; G11; G11C; G11C16/00; G11C8/00; G11C8/08; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
273 words
A nonvolatile semiconductor memory device comprising: a nonvolatile memory cell; a word line connected to said nonvolatile memory cell; a decoder to which an address signal is input; a word line driver having a first node, a second node, an output node, a first P-channel transistor and a first N-channel transistor, a first terminal of said first P-channel transistor being connected to said first node, a second terminal of said first P-channel transistor being connected to said output node, a substrate terminal of said first P-channel transistor being connected to said first node, a substrate terminal of said first N-channel transistor being connected to said second node, and said output node supplying a first predetermined potential to said word line; a second N-channel transistor having a gate terminal to which a second predetermined potential is applied, a first terminal of said second N-channel transistor being connected to said decoder and a second terminal of said second N-channel transistor being connected to a gate terminal of said first P-channel transistor; and a second P-channel transistor having a gate terminal connected to which a predetermined signal is applied, a first terminal of said second P-channel transistor being connected to a gate terminal of said first P channel transistor, a second terminal of said second P-channel transistor being connected to a substrate terminal of said second P-channel transistor, wherein in an erase mode a negative potential is applied to said second node of said word line driver, and a voltage greater than the negative potential is applied to both said first node of said word line driver and the second terminal of said second P-channel transistor.
Claim 2
Dependent Claim
273 words
A nonvolatile semiconductor memory device comprising: a nonvolatile memory cell; a word line connected to said nonvolatile memory cell; a decoder to which an address signal is input; a word line driver having a first node, a second node, an output node, a first P-channel transistor and a first N-channel transistor, a first terminal of said first P-channel transistor being connected to said first node, a second terminal of said first P-channel transistor being connected to said output node, a substrate terminal of said first P-channel transistor being connected to said first node, a substrate terminal of said first N-channel transistor being connected to said second node, and said output node supplying a first predetermined potential to said word line; a second N-channel transistor having a gate terminal to which a second predetermined potential is applied, a first terminal of said second N-channel transistor being connected to said decoder and a second terminal of said second N-channel transistor being connected to a gate terminal of said first P-channel transistor; and a second P-channel transistor having a gate terminal connected to which a predetermined signal is applied, a first terminal of said second P-channel transistor being connected to a gate terminal of said first P channel transistor, a second terminal of said second P-channel transistor being connected to a substrate terminal of said second P-channel transistor, wherein in an erase mode a negative potential is applied to said second node of said word line driver, and a voltage greater than the negative potential is applied to both said first node of said word line driver and the second terminal of said second P-channel transistor.
Claim 3
Dependent Claim
43 words
The nonvolatile semiconductor memory device according to claim 1, wherein said first N-channel transistor is provided on a well region having the negative potential applied thereto and isolated from a substrate on which said semiconductor memory device is formed in said erase mode.
Claim 4
Dependent Claim
33 words
The nonvolatile semiconductor memory device according to claim 2, wherein said well region and said substrate have P-type conductivity and said well region is formed within an N-type well formed in said substrate.
Claim 5
Dependent Claim
16 words
The nonvolatile semiconductor memory device according to claim 1, wherein said decoder comprises an AND gate.
Claim 6
Dependent Claim
131 words
The nonvolatile semiconductor memory device according to claim 1, further comprising a decode select signal decoding circuit for receiving a decode select signal and for outputting a first signal and a second signal which is complementary to the first signal; a transfer gate circuit including a third N-channel transistor connected between said output node and said word line and having a gate electrode supplied with the first signal; and a fourth N-channel transistor connected between said word line and said second node, and having a gate electrode supplied with the second signal, wherein said third N-channel transistor and said fourth N-channel transistor are provided on a well region having the negative potential applied thereto and isolated from a substrate on which said semiconductor memory device is formed in said erase mode.
Claim 7
Dependent Claim
27 words
The nonvolatile semiconductor memory device according to claim 5, wherein said transfer gate circuit includes a third P-channel transistor connected in parallel to said third N-channel transistor.
Claim 8
Dependent Claim
23 words
The nonvolatile semiconductor memory device according to claim 6, wherein said third P-channel transistor has a gate terminal supplied with the second signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-21 | 2003-09-20 | 2004-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-21 | 2007-09-20 | 2008-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-21 | 2011-09-20 | 2012-03-21 | $7700.00 | Window Closed / Lapsed |