Nonvolatile memory array wordline driver circuit with voltage translator circuit

Claim 2

A circuit for selectively applying a supply voltage and a programming voltage to a wordline of a nonvolatile memory array, said circuit comprising: a supply voltage terminal for supplying said supply voltage; a control circuit for respectively providing a reading control signal, a programming control signal, and a programming voltage output for supplying said programming voltage; a read mode subcircuit having an input connected to said supply voltage terminal and having a read mode output for selectively outputting said supply voltage in response to said reading control signal; a program mode subcircuit having an input connected to said programming voltage output and having a program mode output for selectively outputting said programming voltage in response to said programming control signal; a second signal-transistor switch connected between said program mode output and said wordline, said second single-transistor switch having a control input connected to a program enable signal output of said control circuit.

Claim 3

The circuit of claim 1, wherein said program mode subcircuit includes a translator subcircuit having an enabling input coupled to said programming control signal of said control circuit, said translator subcircuit having a translator output; and a switching circuit having a control input connected to said translator output, having an input connected to said programming voltage output, and having an output connected to said program mode output.

Claim 4

The circuit of claim 1, wherein said program mode subcircuit includes a translator subcircuit having an enabling input coupled to said programming control signal of said control circuit, a programming voltage input connected to said programming voltage output of said control circuit, and a translator output, and further includes a switching subcircuit having an input connected to said translator output; and wherein said translator subcircuit selectively couples said translator output to said programming voltage output of said control circuit in response to said programming control signal at said enabling input.

Claim 5

The circuit of claim 1, wherein said memory cell array has a minimum lithographic dimension, wherein said program mode subcircuit includes a translator subcircuit having a field-effect transistor that has a channel length longer than said minimum lithographic dimension of said memory cell array.

Claim 6

The circuit of claim 1, wherein said memory cell array has a minimum lithographic dimension, wherein said read mode subcircuit includes a field-effect transistor that has a channel-length substantially equal to said minimum lithographic dimension of said memory cell array.

Claim 7

The circuit of claim 1, wherein said memory cell array includes memory cells having a first gate insulator thickness, wherein said program mode subcircuit includes a field-effect transistor that has a second gate insulator thickness greater than said first gate insulator thickness.

Claim 8

The circuit of claim 1, wherein said memory cell array includes a memory cell having a first gate insulator thickness that defines a maximum gate insulator thickness for the memory cell array, wherein said read mode subcircuit includes at least one field-effect transistor having a second gate insulator thickness, and wherein said second gate insulator thickness is substantially equal to said first gate insulator thickness.

Claim 9

The circuit of claim 1, wherein said program mode subcircuit and said memory array are formed on a substrate and wherein said program mode subcircuit is formed on said substrate at a distance from said memory cell array.

Claim 10

The circuit of claim 1, wherein said read mode subcircuit and said memory array are formed on a substrate and wherein said read mode subcircuit is formed on said substrate at a distance from said memory ell array.

Claim 11

The circuit of claim 1, wherein said program mode subcircuit includes a translator having first and second translator outputs and having an enabling input, said translator subcircuit comprising: a first transistor of a first conductivity type having a first source-drain, a second source-drain and a gate, said first source-drain connected to said programming voltage output of said control circuit, a second transistor of said first conductivity type having a first source-drain, a second source-drain and a gate, said first source-drain of said second transistor connected to said programming voltage output of said control circuit; a third transistor of said first conductivity-type having a first source-drain, a second source-drain and a gate, said first source-drain of said third transistor connected to said second source-drain of said first transistor, and said gate of said third transistor connected to a high voltage detect output of said control circuit; a fourth transistor of said first conductivity-type having a first source-drain, a second source-drain and a gate, said first source-drain of said fourth transistor connected to said second source-drain of said second transistor, and said gate of said fourth transistor connected to said high voltage detect output of said control circuit; a fifth transistor of said second conductivity-type opposite said first conductivity-type, having a first source-drain, a second source-drain and a gate, said first source-drain of said fifth transistor connected to said second source-drain of said third transistor, to said gate of said second transistor, and to said first translator output and said gate of said fifth transistor connected to said supply voltage terminal; a sixth transistor of said second conductivity-type having a first source-drain, a second source-drain and a gate, said first source-drain of said sixth transistor connected to said second source-drain of said fourth transistor, to said gate of said first transistor, and to said second output of said translator subcircuit and said gate of said sixth transistor connected to said supply voltage terminal; a seventh transistor of said second conductivity-type having a first source-drain, a second source-drain and a gate, said first source-drain of said seventh transistor connected to said second source-drain of said fifth transistor, said second source-drain of said seventh transistor connected to a reference voltage, and said gate of said seventh transistor connected to said enabling input; an inverter having an input connected to said enabling input and having an inverter output; an eighth transistor of said second conductivity-type having a first source-drain, a second source-drain and a gate, said first source-drain of said eighth transistor connected to said second source-drain of said sixth transistor, said second source-drain of said eighth transistor connected to said reference voltage, and said gate of said eighth transistor connected to said inverter output; and a switch circuit having control inputs connected to said first and second translator outputs for selectively connecting said programming voltage output of said control circuit to said program mode output.

Claim 12

The circuit of claim 1, wherein said control circuit includes a half-select voltage output and wherein said program mode subcircuit includes: a translator subcircuit having an enabling input coupled to said programming control signal, said translator subcircuit having two translator outputs; and a switching circuit having two control inputs respectively connected to said two translator outputs, having two inputs respectively connected to said programming voltage output of said control circuit and said half-select voltage output of said control circuit, and having a switching output connected to said program mode output.

Claim 13

The circuit of claim 1, wherein said control circuit includes a half-select voltage output and wherein said program mode subcircuit includes: a translator subcircuit having an enabling input coupled to said programming control signal, said translator subcircuit having first and second translator outputs; and a switching circuit comprising: a first transistor having a first source-drain, a second source-drain and a gate, said gate connected to said first translator output and said first source-drain connected to said half-select voltage output of said control circuit; and a second transistor having a first source-drain, a second source-drain and a gate, said gate of said second transistor connected to said second translator output, said first source-drain of said second transistor connected to said programming voltage output of said control circuit, said second source-drain of said second transistor connected to said second source-drain of said first transistor and to said program mode output.

Claim 14

The circuit of claim 1, wherein said circuit for applying supply and programming voltage also applies erasing voltages to said wordline; wherein said control circuit includes a half-select voltage output and an erase signal output and wherein said program mode subcircuit includes: a translator subcircuit having an enabling input coupled to said programming control signal, said translator subcircuit having first and second translator outputs; and a switching circuit comprising: a first transistor having a first source-drain, a second source-drain and a gate, said gate connected to said first translator output and said first source-drain connected to said half-select voltage output of said control circuit; a second transistor having a first source-drain, a second source-drain and a gate, said gate of said second transistor connected to said second translator output, said second source-drain of said second transistor connected to said second source-drain of said first transistor and to said program mode output; and a third transistor having a first source-drain, a second source-drain and a gate, said gate of said third transistor connected to said erase signal output of said control circuit, said first source-drain of said third transistor connected to said programming voltage output of said control circuit, said second source-drain of said third transistor connected to said first source-drain of said second transistor.

Claim 15

The circuit of claim 1, wherein said first and second single-transistor switches are gated field-effect transistors.

Claim 16

The circuit of claim 1, wherein said first single-transistor switch is a field-effect transistor having a first source-drain, a second source-drain and a gate, wherein said first source-drain is connected to said read-mode output, said second source-drain is connected to said wordline, and said gate is connected to said read enable output of said control circuit.

Claim 17

The circuit of claim 1, wherein said second single-transistor switch is a field-effect transistor having a first source-drain, a second source-drain and a gate, wherein said first source-drain is connected to said program mode output, said second source-drain is connected to said wordline, and said gate is connected to said program enable output of said control circuit.

Claim 18

The circuit of claim 1, wherein said circuit for applying supply and programming voltages also applies erasing voltages to said wordline, wherein said program mode subcircuit has an enabling input and said circuit for applying supply and programming voltages further includes: a negative charge pump having a control input and having an erasing voltage output, said control input of said negative charge pump connected to said enabling input, and a third single-transistor switch connected between said erasing voltage output of said negative charge pump and said wordline, said third single-transistor switch having a control input connected to said wordline.

Claim 19

The circuit of claim 1, wherein said circuit for applying supply and programming voltages also applies erasing voltages to said wordline, and wherein said program mode subcircuit has an enabling input and said circuit for applying supply and programming voltages further includes: a negative charge pump having a control input and having an erasing voltage output, said control input of said negative charge pump connected to said enabling input; and a field effect transistor having a first source-drain, a second source-drain and a gate, wherein said first source-drain is connected to said erasing voltage output of said negative charge pump, and said second source-drain and gate are connected to said wordline.

Claim 20

A translator circuit for translating a supply-voltage-level signal to a programming-voltage-level signal, said translator circuit having first and second outputs, an enabling input, a supply voltage input, a programming voltage input, a reference voltage input, and a high-voltage detect input; said translator circuit comprising: a first transistor of a first conductivity type including first and second source-drains and a gate, said first source-drain connected to said programming voltage input; a second transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said second transistor connected to said programming voltage input; a third transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said third transistor connected to said second source-drain of said first transistor, and said gate of said third transistor connected to said high voltage detect input; a fourth transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said fourth transistor connected to said second source-drain of said second transistor, and said gate of said fourth transistor connected to said high voltage detect input; a fifth transistor of a second conductivity-type opposite said first conductivity-type, including first and second source-drains and a gate, said first source-drain of said fifth transistor connected to said second source-drain of said third transistor, to said gate of said second transistor, and to said first output of said translator circuit and said gate of said fifth transistor connected to said supply voltage input; a sixth transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said sixth transistor connected to said second source-drain of said fourth transistor, to said gate of said first transistor, and to said second output of said translator circuit and said gate of said sixth transistor connected to said supply voltage input; a seventh transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said seventh transistor connected to said second source-drain of said fifth transistor, said second source-drain of said seventh transistor connected to said reference voltage input, and said gate of said seventh transistor connected to said enabling input; an inverter having an input connected to said enabling input and having an output; an eighth transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said eighth transistor connected to said second source-drain of said sixth transistor, said second source-drain of said eighth transistor connected to said reference voltage input, and said gate of said eighth transistor connected to said output of said inverter.

Claim 21

A translator circuit for translating a supply-voltage-level signal to a programming-voltage-level signal, said translator circuit having first and second outputs, an enabling input, a supply voltage input, a programming voltage input, a reference voltage input, and a high-voltage detect input; said translator circuit comprising: a first transistor of a first conductivity type including first and second source-drains and a gate, said first source-drain connected to said programming voltage input; a second transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said second transistor connected to said programming voltage input; a third transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said third transistor connected to said second source-drain of said first transistor, and said gate of said third transistor connected to said high voltage detect input; a fourth transistor of said first conductivity-type including first and second source-drains and a gate, said first source-drain of said fourth transistor connected to said second source-drain of said second transistor, and said gate of said fourth transistor connected to said high voltage detect input; a fifth transistor of a second conductivity-type opposite said first conductivity-type, including first and second source-drains and a gate, said first source-drain of said fifth transistor connected to said second source-drain of said third transistor, to said gate of said second transistor, and to said first output of said translator circuit and said gate of said fifth transistor connected to said supply voltage input; a sixth transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said sixth transistor connected to said second source-drain of said fourth transistor, to said gate of said first transistor, and to said second output of said translator circuit and said gate of said sixth transistor connected to said supply voltage input; a seventh transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said seventh transistor connected to said second source-drain of said fifth transistor, said second source-drain of said seventh transistor connected to said reference voltage input, and said gate of said seventh transistor connected to said enabling input; an inverter having an input connected to said enabling input and having an output; an eighth transistor of said second conductivity-type including first and second source-drains and a gate, said first source-drain of said eighth transistor connected to said second source-drain of said sixth transistor, said second source-drain of said eighth transistor connected to said reference voltage input, and said gate of said eighth transistor connected to said output of said inverter.

Claim 22

The translator circuit of claim 19, wherein said first conductivity-type is P-type and said second conductivity-type is N-type.

Claim 23

The translator circuit of claim 19, wherein the translator circuit has a transistor having a first channel length, and wherein the translator circuit includes a second transistor having a channel length that is longer than said first channel length.

Claim 24

The translator circuit of claim 19, wherein said translator circuit has a transistor having a first gate insulator thickness, and wherein said translator circuit has a second said transistor having a gate insulator that is thicker than said first gate insulator thickness.