US4583205A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable memory circuit with an improved programming voltage applying circuit
Assignee: NEC Electronics Corp
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Filing: 1983-09-16
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Granted: 1986-04-15
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Expires: 2003-09-16
Abstract
Abstract A programmable memory circuit adapted to access a memory comprises a decoder responsive to address input signals, an access line, a transfer gate connected between the decoder and the access line, and a selective voltage supply circuit connected to the access line. The transfer gate is responsive to a read/write switch signal to connect the decoder to the access line in the read mode and disconnect the decoder from the access line in the write mode. The selective voltage supply circuit is also responsive to the read/write switch signal to provide on the access line different voltage levels in accordance with read/write mode. The access line assumes, in the read mode, one voltage level which is equal to the level of the output signal from the decoder and in the write mode the other voltage level.
Inventors
- 👤 Takeshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:32
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
162 words
A programmable memory circuit comprising: a decoder responsive to address input signals for addressing the memory; an access line for the memory; transfer gate means connected between said decoder and said access line and responsive to a read/write switch signal for connecting or disconnecting the output of the decoder to said access line; and selective voltage supply circuit means connected to said access line and responsive to selection of said access line to provide different voltage levels on said access line in accordance with a read/write mode, said selective voltage supply circuit means including a first terminal, a switching means coupled between said first terminal and said access line, a voltage selecting means responsive to said read/write switch signal for selectively applying one of a read power supply voltage or a write power supply voltage to said first terminal, and control means responsive to a level of said access line for selectively enabling said switching means when said access line is selected.
Claim 2
Dependent Claim
162 words
A programmable memory circuit comprising: a decoder responsive to address input signals for addressing the memory; an access line for the memory; transfer gate means connected between said decoder and said access line and responsive to a read/write switch signal for connecting or disconnecting the output of the decoder to said access line; and selective voltage supply circuit means connected to said access line and responsive to selection of said access line to provide different voltage levels on said access line in accordance with a read/write mode, said selective voltage supply circuit means including a first terminal, a switching means coupled between said first terminal and said access line, a voltage selecting means responsive to said read/write switch signal for selectively applying one of a read power supply voltage or a write power supply voltage to said first terminal, and control means responsive to a level of said access line for selectively enabling said switching means when said access line is selected.
Claim 3
Dependent Claim
43 words
The programmable memory circuit according to claim 1 wherein said decoder includes a main decoder in the form of a NAND gate and a sub-decoder in the form of a complementary logic circuit, and said transfer gate includes a depletion type semiconductor element.
Claim 4
Dependent Claim
62 words
The programmable memory circuit according to claim 1 wherein the output of said decoder selectively assumes a level of the read power supply voltage or a ground level, and said transfer gate means connects the output of said decoder to said access line in the read mode and disconnects the output of said decoder from said access line in the write mode.
Claim 5
Dependent Claim
75 words
The programmable memory circuit according to claim 1 wherein said voltage selecting means includes a second voltage terminal for receiving the read power supply voltage, a third terminal for receiving the write power supply voltage, a first switch coupled between said second terminal and said first terminal, a second switch coupled between said third terminal and said first terminal, and means responsive to said read/write switch signal for selectively enabling said first and second switches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |