US4455629A — Complementary metal-insulated semiconductor memor…

Claim 1

Independent Claim 175 words

A CMIS memory decoder for selecting each set of 2 m (where m is a positive integer) word lines operatively connected to a memory array operatively connected to bit lines, said decoder having connected thereto an input gate having an output and receiving address signals having a first m bit portion and a second bit portion, the second bit portion being used for simultaneously specifying the 2 m word lines and the first bit portion for generating clock pulses, said decoder comprising: CMIS inverters, operatively connected to the output of the input gate, and each inverter being driven by the corresponding clock pulse generated in dependence upon the first m bit portion of said address signal, an output of each of the inverters being operatively connected to the corresponding one of the 2 m word lines; and 2 m -1 pull-down transistors for each of the 2 m word lines and operatively connected to the respective word line and each having a gate operatively connected to one of the remaining 2 m -1 word lines.

Claim 2

Dependent Claim 175 words

A CMIS memory decoder for selecting each set of 2 m (where m is a positive integer) word lines operatively connected to a memory array operatively connected to bit lines, said decoder having connected thereto an input gate having an output and receiving address signals having a first m bit portion and a second bit portion, the second bit portion being used for simultaneously specifying the 2 m word lines and the first bit portion for generating clock pulses, said decoder comprising: CMIS inverters, operatively connected to the output of the input gate, and each inverter being driven by the corresponding clock pulse generated in dependence upon the first m bit portion of said address signal, an output of each of the inverters being operatively connected to the corresponding one of the 2 m word lines; and 2 m -1 pull-down transistors for each of the 2 m word lines and operatively connected to the respective word line and each having a gate operatively connected to one of the remaining 2 m -1 word lines.

Claim 3

Dependent Claim 29 words

A CMIS memory decoder as set forth in claim 1, wherein said 2 m-1 pull-down transistors are N-channel MIS transistors, and are connected between each word line and ground.

Claim 4

Dependent Claim 72 words

A CMIS memory decoder as set forth in claim 2, wherein each of said CMIS inverters comprises a pair of transistors connected in series both having gates, both gates being commonly connected to the output of said input gate, one said pair of transistors receiving one of the clock pulses and being a P-channel MIS transistor, and the other of said pair of transistors being an N-channel MIS transistor connected to ground.

Claim 5

Dependent Claim 40 words

A CMIS memory decoder as set forth in claim 3, wherein said CMIS inverters and said pull-down transistors are formed inside the width between one end of the group of the 2 m word lines and the other end thereof.

Claim 6

Dependent Claim 94 words

A memory decoder, operatively connectable to receive address signals, for a memory cell array having word lines, comprising: control means, operatively connectable to receive the address signals, for generating control signals for selecting the word lines in dependence upon the address signals; pull-up means, operatively connected to said control means and the word lines, for pulling the selected word lines to a first voltage in dependence upon the control signals; and pull-down means, operatively connected to the word lines, for pulling non-selected word lines to a second voltage in dependence on the first voltage.

Claim 7

Dependent Claim 94 words

A memory decoder, operatively connectable to receive address signals, for a memory cell array having word lines, comprising: control means, operatively connectable to receive the address signals, for generating control signals for selecting the word lines in dependence upon the address signals; pull-up means, operatively connected to said control means and the word lines, for pulling the selected word lines to a first voltage in dependence upon the control signals; and pull-down means, operatively connected to the word lines, for pulling non-selected word lines to a second voltage in dependence on the first voltage.

Claim 8

Dependent Claim 88 words

A memory decoder as set forth in claim 5, wherein the number of word lines is equal to n where n is an integer greater than or equal to 2, and wherein said pull-down means comprises n pull-down transistor sets, each set operatively connected to a respective word line and each set comprising n-1 pull-down transistors operatively connected to the respective word line, each of the n-1 pull-down transistors operatively connected to the same word line being controlled by a different one of the remaining n-1 word lines.

Claim 9

Dependent Claim 28 words

A memory decoder as set forth in claim 6, wherein said pull-up means comprises n inverters operatively connected to said control means and said n word lines respectively.

Claim 10

Dependent Claim 45 words

A memory decoder as set forth in claim 7, wherein each of said n inverters comprises: a first transistor operatively connected to said control means and the respective word line; and a second transistor operatively connected to said control means and the respective word line.

Claim 11

Dependent Claim 68 words

A memory decoder as set forth in claim 8, wherein said control means comprises: a NAND circuit operatively connected to said first and second transistors of each of said n inverters and to receive a part of said address signals; and n AND circuits each operatively connected to a respective one of said first transistors of said n inverters and to receive the remainder of said address signals.

Claim 12

Dependent Claim 17 words

A memory decoder as set forth in claim 9, wherein said first transistor is a p-channel transistor.

Claim 13

Dependent Claim 21 words

A memory decoder as set forth in claim 10, wherein said n-1 pull-down transistors and said second transistor are n-channel devices.

Claim 14

Dependent Claim 13 words

A memory decoder as set forth in claim 11, wherein n equals two.

Claim 15

Dependent Claim 13 words

A memory decoder as set forth in claim 11, wherein n equals four.

Claim 16

Dependent Claim 30 words

A memory decoder as set forth in claim 13, wherein said three pull-down transistors operatively connected to one of the four word lines are operatively connected to the second voltage.

Claim 17

Dependent Claim 20 words

A memory decoder as set forth in claim 14, wherein each of said four AND circuits generate the first voltage.

Claim 18

Dependent Claim 40 words

A memory decoder as set forth in claim 15, wherein said four word lines define an area width on a semiconductor substrate, and wherein said first and second transistors and said twelve pull-down transistors are formed within said area width.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1987-06-19	1987-12-19	1988-06-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1991-06-19	1991-12-19	1992-06-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1995-06-19	1995-12-19	1996-06-19	$7700.00	Window Closed / Lapsed

Complementary metal-insulated semiconductor memory decoder

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