US3909808A
Expired / Lapsed
US
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Minimum pitch mosfet decoder circuit configuration
Assignee: International Business Machines Corp
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Filing: 1974-12-23
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Granted: 1975-09-30
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Expires: 1994-12-23
Abstract
Abstract MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition, the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.
Inventors
- 👤 William Hugh Cochran
- 👤 Dale Arthur Heuer
- 👤 Michael James Sheehan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:39
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C8/00; G11C8/10; G11C8/12; G11C8/14; H; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
495 words
A MOSFET decoder circuit configuration for enhancing ROS memory densities for obtaining decoded output lines on a narrower pitch than conventional decoder circuits, wherein said decoded output lines of said conventional decoder are increased by a binary factor of 21 comprising in combination: an external system clock control for generating adecoder clock pulse and an array flush pulse; a conventional decoder circuit driven by a plurality of decoder address inputs (An 1 . . . An n) and said decoder clock pulse to obtain a valid decoding address on a single output line of said conventional decoder; a complement array select device connected to said single output line of said conventional decoder; an array select device connected to said single output line of said conventional decoder; an address complement generator driven by a generator address input (An) to obtain a generator address output (An) at the output of said address complement generator for driving said complement array select device to switch said complement array select device when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining the complement of said valid decoded address at the output line of said complement array select device; an address generator driven by said generator address output (An) of said address complement generator to obtain a generator address output (An) at the output of said address generator for driving said array select device to switch said array select device when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining said valid decoded address at the output line of said array select device; a ROS memory array having a memory cell accessed by means of said output line of said complement array select device, and said ROS memory array having another memory cell accessed by means of said output line of said array select device, said memory cells being selected alternately be means of said complement array select device and said array select device; a complement array flush device connected to said output line of said complement array select device for flushing the parasitic capacitance from said output line of said complement array select device readying said output line for a subsequent memory access, said complement array flush device being switched by said array flush pulse from said external system clock control; an array flush device connected to said output line of said array select device for flushing the parasItic capacitance from said output line of said array select device readying said output line for a subsequent memory access, said array flush device being switched by said array flush pulse from said external system clock control; whereby said single output line of said conventional decoder is increased by a binary factor of 21 allowing a narrower pitch to be achieved so as to match said output lines of said complement array select device and said array select device to said ROS memory array input lines.
Claim 2
Dependent Claim
495 words
A MOSFET decoder circuit configuration for enhancing ROS memory densities for obtaining decoded output lines on a narrower pitch than conventional decoder circuits, wherein said decoded output lines of said conventional decoder are increased by a binary factor of 21 comprising in combination: an external system clock control for generating adecoder clock pulse and an array flush pulse; a conventional decoder circuit driven by a plurality of decoder address inputs (An 1 . . . An n) and said decoder clock pulse to obtain a valid decoding address on a single output line of said conventional decoder; a complement array select device connected to said single output line of said conventional decoder; an array select device connected to said single output line of said conventional decoder; an address complement generator driven by a generator address input (An) to obtain a generator address output (An) at the output of said address complement generator for driving said complement array select device to switch said complement array select device when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining the complement of said valid decoded address at the output line of said complement array select device; an address generator driven by said generator address output (An) of said address complement generator to obtain a generator address output (An) at the output of said address generator for driving said array select device to switch said array select device when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining said valid decoded address at the output line of said array select device; a ROS memory array having a memory cell accessed by means of said output line of said complement array select device, and said ROS memory array having another memory cell accessed by means of said output line of said array select device, said memory cells being selected alternately be means of said complement array select device and said array select device; a complement array flush device connected to said output line of said complement array select device for flushing the parasitic capacitance from said output line of said complement array select device readying said output line for a subsequent memory access, said complement array flush device being switched by said array flush pulse from said external system clock control; an array flush device connected to said output line of said array select device for flushing the parasItic capacitance from said output line of said array select device readying said output line for a subsequent memory access, said array flush device being switched by said array flush pulse from said external system clock control; whereby said single output line of said conventional decoder is increased by a binary factor of 21 allowing a narrower pitch to be achieved so as to match said output lines of said complement array select device and said array select device to said ROS memory array input lines.
Claim 3
Dependent Claim
89 words
A decoder configuration in accordance with claim 1 wherein: said address complement generator switching is accomplished by an address switch, said address switch being a MOSFET having a gate connected to said generator address input (An) and a source connected to ground; and said address complement generator further comprising a load device, said load device being a MOSFET having a gate connected to a drain and a voltage (VDD) and a source connected to a drain of said address switch forming said output line of said address complement generator.
Claim 4
Dependent Claim
89 words
A decoder configuration in accordance with claim 1 wherein: said address generator switching is accomplished by an address switch, said address switch being a MOSFET having a gate connected to said output line of said address complement generator and a source connected to ground; and said address complement generator further comprising a load device, said load device being MOSFET having a gate connected to a drain and a voltage (VDD) and a source connected to a drain of said address switch forming said output line of said address generator.
Claim 5
Dependent Claim
53 words
A decoder configuration in accordance with claim 1 wherein said complement array select device is a MOSFET having a drain connected to said output of said conventional decoder, a gate connected to said output of said address complement generator and a source connected to said output line of said complement array select device.
Claim 6
Dependent Claim
50 words
A decoder configuration in accordance with claim 1 wherein said array select device is a MOSFET having a drain connected to said output of said conventional decoder, a gate connected to said output of said address generator and a source connected to said output line of said array select device.
Claim 7
Dependent Claim
45 words
A decoder configuration in accordance with claim 1 wherein said complement array flush device is a MOSFET having a drain connected to said output line of said complement array select device, a gate connected to said array flush pulse and a source connected to ground.
Claim 8
Dependent Claim
43 words
A decoder configuration in accordance with claim 1 wherein said array flush device is a MOSFET having a drain connected to said output line of said array select device, a gate connected to said array flush pulse and a source connected to ground.
Claim 9
Dependent Claim
477 words
A MOSFET decoder circuit configuration for increasing the decoded output lines of a conventional decoder by a binary factor of 2n comprising in combination: a conventional decoder circuit driven by a plurality of decoder address inputs (An 1 . . . An n) and a decoder clock pulse to obtain a valid decoded address (A0) on a single output line of said conventional decoder; a plurality of 2n 1 complement array select devices connected in parallel to said single output line of said conventional decoder; a plurality of 2n 1 array select devices connected in parallel to said single output line of said conventional decoder; a plurality of 2n 1 address complement generators driven by a plurality of generator address inputs (An . . . An n) to obtain a plurality of generator address outputs (A1 . . . A2 ) at the outputs of said plurality of address complement generators for driving said plurality of complement array select devices to switch said plurality of complement array select devices when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining a plurality of complement valid decoded addresses (A1 . . . A2 ) at the output lines of said plurality of complement array select devices; a plurality of 2n 1 address generators driven by said plurality of generator address outputs (A1 . . . A2 ) of said plurality of address complement generators to obtain a plurality of generator address outputs (A1 . . . A2 ) at the outputs of said plurality of address generators for driving said plurality of array select devices to switch said plurality of array select devices when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining a plurality of valid decoded addresses (A1 . . . A2 ) at the output lines of said plurality of array select devices; a plurality of complement array flush devices one each being connected to said output lines of said plurality of complement array select devices for flushing parasitic capacitance from said output lines of said plurality of complement array select devices, said plurality of complement array select devices being driven by an array flush pulse; a plurality of array flush device one each being connected to said output lines of said plurality of array select devices for flushing parasitic capacitance from said output lines of said plurality of array select devices, said plurality of array select devices being driven by said array flush pulse; whereby said single output line of said conventional decoder is increased by a binary factor of 2n allowing a narrower pitch to be achieved so as to enable matching of said output lines of said plurality of complement array select devices and said plurality of array select devices to a ROS memory array input lines.
Claim 10
Dependent Claim
477 words
A MOSFET decoder circuit configuration for increasing the decoded output lines of a conventional decoder by a binary factor of 2n comprising in combination: a conventional decoder circuit driven by a plurality of decoder address inputs (An 1 . . . An n) and a decoder clock pulse to obtain a valid decoded address (A0) on a single output line of said conventional decoder; a plurality of 2n 1 complement array select devices connected in parallel to said single output line of said conventional decoder; a plurality of 2n 1 array select devices connected in parallel to said single output line of said conventional decoder; a plurality of 2n 1 address complement generators driven by a plurality of generator address inputs (An . . . An n) to obtain a plurality of generator address outputs (A1 . . . A2 ) at the outputs of said plurality of address complement generators for driving said plurality of complement array select devices to switch said plurality of complement array select devices when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining a plurality of complement valid decoded addresses (A1 . . . A2 ) at the output lines of said plurality of complement array select devices; a plurality of 2n 1 address generators driven by said plurality of generator address outputs (A1 . . . A2 ) of said plurality of address complement generators to obtain a plurality of generator address outputs (A1 . . . A2 ) at the outputs of said plurality of address generators for driving said plurality of array select devices to switch said plurality of array select devices when said valid decoded address is present at said single output line of said conventional decoder thereby obtaining a plurality of valid decoded addresses (A1 . . . A2 ) at the output lines of said plurality of array select devices; a plurality of complement array flush devices one each being connected to said output lines of said plurality of complement array select devices for flushing parasitic capacitance from said output lines of said plurality of complement array select devices, said plurality of complement array select devices being driven by an array flush pulse; a plurality of array flush device one each being connected to said output lines of said plurality of array select devices for flushing parasitic capacitance from said output lines of said plurality of array select devices, said plurality of array select devices being driven by said array flush pulse; whereby said single output line of said conventional decoder is increased by a binary factor of 2n allowing a narrower pitch to be achieved so as to enable matching of said output lines of said plurality of complement array select devices and said plurality of array select devices to a ROS memory array input lines.
References Cited (Backward Citations)
US3821715A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |