High speed input receiver and wordline driver circuit

Claim 1

An interface circuit for providing first and second output logic signals at respective first and second wordlines of a memory array in response to an input logic signal, said second output logic signal being the inverse of said first output logic signal, said circuit comprising: inverter means for producing inverted and non-inverted logic signals in response to said input logic signal; first and second buffer circuits each comprising a pair of complementary transistors coupled in an inverter configuration between first and second operating potentials, said first buffer circuit being coupled to receive said non-inverted logic signal and produce said second output logic signal on said second wordline, and said second buffer circuit being coupled to receive said inverted logic signal and produce said first output logic signal on said first wordline in response thereto; wherein said first and second buffer circuits each include a means for isolating a high potential appearing on said first and second wordlines from said first and second operating potentials; said first buffer circuit further comprising an n-channel transistor coupled between said second wordline and said first operating potential through said isolating means, said n-channel transistor having its gate coupled to an inverted logic signal, said n-channel transistor increasing the low-to-high transition of said second output logic signal in response to a high-to-low transition of said input logic signal.