EP0345791A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory
Assignee: Toshiba Corp
•
Filing: 1989-06-08
•
Granted: —
•
Expires: 2009-06-08
Abstract
Abstract A memory cell array (MA) includes a matrix array of a plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃). These memory cells are nonvolatile transistors. The memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each row of the memory array (MM), are coupled with a plurality of word lines (WL0 to WL3). The word lines are selected by a row decoder (10) made up of a plurality of partial decoders (10₀ to 10₃). In this case, a constant voltage output circuit (20), which is provided at the outputs of the partial decoders 10₀ to 10₃) of the row decoder (10), outputs a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by the outputs of the partial decoders (10₀ to 10₃).
Inventors
- 👤 Tadashi Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 08:19
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
261 words
A nonvolatile semiconductor memory comprising: a memory cell array (MA) in which a plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) are arrayed in a matrix fashion, each said memory cell including a nonvolatile transistor; a plurality of word lines (WL0 to WL3) coupled with the gates of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each row of said memory array (MM); a row decoder (10) including a plurality of partial decoders (10₀ to 10₃) for selecting said plurality of word lines; a plurality of bit lines (BL0 to BL3) coupled with the drains of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each column of said memory array (MM); a column decoder (50) including a plurality of partial decoders (50₀ to 50₃) for selecting said plurality of bit lines (BL0 to BL3); and a sense amplifier (30) to be coupled with one of said plurality of bit lines (BL0 to BL3) selected by an output signal of said column decoder (50), characterized by further comprising: a constant voltage output circuit (20) for receiving the outputs of said partial decoders (10₀ to 10₃) of said row decoder (50), and for outputting a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by said partial decoders (10₀ to 10₃).
Claim 2
Dependent Claim
261 words
A nonvolatile semiconductor memory comprising: a memory cell array (MA) in which a plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) are arrayed in a matrix fashion, each said memory cell including a nonvolatile transistor; a plurality of word lines (WL0 to WL3) coupled with the gates of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each row of said memory array (MM); a row decoder (10) including a plurality of partial decoders (10₀ to 10₃) for selecting said plurality of word lines; a plurality of bit lines (BL0 to BL3) coupled with the drains of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each column of said memory array (MM); a column decoder (50) including a plurality of partial decoders (50₀ to 50₃) for selecting said plurality of bit lines (BL0 to BL3); and a sense amplifier (30) to be coupled with one of said plurality of bit lines (BL0 to BL3) selected by an output signal of said column decoder (50), characterized by further comprising: a constant voltage output circuit (20) for receiving the outputs of said partial decoders (10₀ to 10₃) of said row decoder (50), and for outputting a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by said partial decoders (10₀ to 10₃).
Claim 3
Dependent Claim
78 words
The nonvolatile semiconductor memory according to claim 1, characterized in that said constant voltage output circuit (20) includes a plurality of MOS transistors (22), each said MOS transistor (22) is of the depletion type (22) whose source-drain path is inserted in series between an output terminal of the corresponding partial decoder (10₀ to 10₃) in said row decoder (10) and the corresponding word line (WL0 to WL3), and whose gate is coupled with a second power source voltage.
Claim 4
Dependent Claim
75 words
The nonvolatile semiconductor memory according to claim 2, characterized in that a threshold voltage of each said MOS transistor (22) is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃).
Claim 5
Dependent Claim
142 words
The nonvolatile semiconductor memory according to claim 1, characterized in that said constant voltage output circuit (20) includes: a plurality of first MOS transistors (22), each said first MOS transistor (22) being of the depletion type whose source-drain path is connected at one end to an output terminal of the corresponding partial decoder (10₀ to 10₃) in said row decoder (10), and whose gate is coupled with a second power source voltage; and a plurality of second MOS transistors (25), each said second MOS transistor (25) being of the depletion type whose source-drain path is inserted in series between the output terminal of the corresponding partial decoder (10₀ to 10₃) in said row decoder (10) and the corresponding word line (WL0 to WL3), and whose gate is coupled with other end of the source-drain path of a corresponding first MOS transistor (22).
Claim 6
Dependent Claim
76 words
The nonvolatile semiconductor memory according to claim 4, characterized in that a threshold voltage of each said MOS transistor (22, 25) is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃).
Claim 7
Dependent Claim
22 words
The nonvolatile semiconductor memory according to claim 2 or 4, characterized in that said second power source voltage is a ground voltage.
Claim 8
Dependent Claim
259 words
An EPROM comprising: a memory cell array (MA) in which a plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) are arrayed in a matrix fashion, each said memory cell including a nonvolatile transistor; a plurality of word lines (WL0 to WL3) coupled with the gates of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each row of said memory array (MM); a row decoder (10) including a plurality of partial decoders (10₀ to 10₃) for selecting said plurality of word lines; a plurality of bit lines (BL0 to BL3) coupled with the drains of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each column of said memory array (MM); a column decoder (50) including a plurality of partial decoders (50₀ to 50₃) for selecting said plurality of bit lines (BL0 to BL3); and a sense amplifier (30) to be coupled with one of said plurality of bit lines (BL0 to BL3) selected by an output signal of said column decoder (50), characterized by further comprising: a constant voltage output circuit (20) for receiving the outputs of said partial decoders (10₀ to 10₃) of said row decoder (50), and for outputting a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by said partial decoders (10₀ to 10₃).
Claim 9
Dependent Claim
259 words
An EPROM comprising: a memory cell array (MA) in which a plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) are arrayed in a matrix fashion, each said memory cell including a nonvolatile transistor; a plurality of word lines (WL0 to WL3) coupled with the gates of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each row of said memory array (MM); a row decoder (10) including a plurality of partial decoders (10₀ to 10₃) for selecting said plurality of word lines; a plurality of bit lines (BL0 to BL3) coupled with the drains of said plurality of memory cells (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃) which are arrayed in each column of said memory array (MM); a column decoder (50) including a plurality of partial decoders (50₀ to 50₃) for selecting said plurality of bit lines (BL0 to BL3); and a sense amplifier (30) to be coupled with one of said plurality of bit lines (BL0 to BL3) selected by an output signal of said column decoder (50), characterized by further comprising: a constant voltage output circuit (20) for receiving the outputs of said partial decoders (10₀ to 10₃) of said row decoder (50), and for outputting a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by said partial decoders (10₀ to 10₃).
Claim 10
Dependent Claim
76 words
The EPROM according to claim 7, characterized in that said constant voltage output circuit (20) includes a plurality of MOS transistors (22), each said MOS transistor (22) is of the depletion type (22) whose source-drain path is inserted in series between an output terminal of the corresponding partial decoder 10₀ to 10₃) in said row decoder (10) and the corresponding word line (WL0 to WL3), and whose gate is coupled with a second power source voltage.
Claim 11
Dependent Claim
73 words
The EPROM according to claim 8, characterized in that a threshold voltage of each said MOS transistor (22) is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃).
Claim 12
Dependent Claim
140 words
The EPROM according to claim 7, characterized in that said constant voltage output circuit (20) includes: a plurality of first MOS transistors (22), each said first MOS transistor (22) being of the depletion type whose source-drain path is connected at one end to an output terminal of the corresponding partial decoder (10₀ to 10₃) in said row decoder (10), and whose gate is coupled with a second power source voltage; and a plurality of second MOS transistors (25), each said second MOS transistor (25) being of the depletion type whose source-drain path is inserted in series between the output terminal of the corresponding partial decoder (10₀ to 10₃) in said row decoder (10) and the corresponding word line (WL0 to WL3), and whose gate is coupled with other end of the source-drain path of a corresponding first MOS transistor (22).
Claim 13
Dependent Claim
74 words
The EPROM according to claim 10, characterized in that a threshold voltage of each said MOS transistor (22, 25) is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell (MC₀₀ to MC₀₃, MC₁₀ to MC₁₃, MC₂₀ to MC₂₃, MC₃₀ to MC₃₃).
Claim 14
Dependent Claim
20 words
The EPROM according to claim 8 or 10, characterized in that said second power source voltage is a ground voltage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.