Patent US6018249A successfully refreshed from Google Patents.
US6018249A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test system with mechanical alignment for semiconductor chip scale packages and dice
Assignee: Micron Technology Inc
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Filing: 1997-12-11
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Granted: 2000-01-25
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Expires: 2017-12-11
Abstract
Abstract A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.
Inventors
- 👤 Salman Akram
- 👤 Warren M. Farnworth
- 👤 David R. Hembree
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:25
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/04
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
91 words
A test system for semiconductor components comprising: a semiconductor component comprising a plurality of external contact bumps and an alignment member; an interconnect comprising a plurality of contact members configured to make non-bonded electrical connections with the contact bumps, each contact member comprising an indentation sized to retain and electrically contact a contact bump, the indentation comprising a sloped sidewall for guiding the contact bums into the indentation; and an alignment fixture on the interconnect comprising a surface configured to engage the alignment member to align the component with the interconnect.
Claim 2
Dependent Claim
91 words
A test system for semiconductor components comprising: a semiconductor component comprising a plurality of external contact bumps and an alignment member; an interconnect comprising a plurality of contact members configured to make non-bonded electrical connections with the contact bumps, each contact member comprising an indentation sized to retain and electrically contact a contact bump, the indentation comprising a sloped sidewall for guiding the contact bums into the indentation; and an alignment fixture on the interconnect comprising a surface configured to engage the alignment member to align the component with the interconnect.
Claim 3
Dependent Claim
26 words
The test system of claim 1 wherein the alignment fixture comprises a polymer layer on the interconnect and the surface comprises an opening in the layer.
Claim 4
Dependent Claim
17 words
The test system of claim 1 wherein the alignment member comprises a beveled edge on the component.
Claim 5
Dependent Claim
25 words
The test system of claim 1 wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
Claim 6
Dependent Claim
86 words
A test system for semiconductor components comprising: a semiconductor component comprising a plurality of contact bumps and an alignment member; an interconnect comprising a plurality of indentations covered with conductive layers, the indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; and an alignment fixture comprising a polymer layer on the interconnect comprising an opening with a surface for engaging the alignment member to align the contact bumps with the indentations.
Claim 7
Dependent Claim
86 words
A test system for semiconductor components comprising: a semiconductor component comprising a plurality of contact bumps and an alignment member; an interconnect comprising a plurality of indentations covered with conductive layers, the indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; and an alignment fixture comprising a polymer layer on the interconnect comprising an opening with a surface for engaging the alignment member to align the contact bumps with the indentations.
Claim 8
Dependent Claim
21 words
The test system of claim 5 wherein the alignment member comprises a beveled edge formed along a periphery of the component.
Claim 9
Dependent Claim
25 words
The test system of claim 5 wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
Claim 10
Dependent Claim
119 words
A test system for semiconductor components comprising: a component comprising a plurality of contact bumps in a arid array and at least one alignment member; a base configured to retain the component comprising a plurality of external contacts connectable to test circuitry; an interconnect on the base comprising a plurality of contact members in electrical communication with the external contacts on the base, the contact members comprising indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; and an alignment fixture on the interconnect comprising a surface configured to engage the alignment member on the component to align the contact bumps to the contact members.
Claim 11
Dependent Claim
119 words
A test system for semiconductor components comprising: a component comprising a plurality of contact bumps in a arid array and at least one alignment member; a base configured to retain the component comprising a plurality of external contacts connectable to test circuitry; an interconnect on the base comprising a plurality of contact members in electrical communication with the external contacts on the base, the contact members comprising indentations configured to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; and an alignment fixture on the interconnect comprising a surface configured to engage the alignment member on the component to align the contact bumps to the contact members.
Claim 12
Dependent Claim
19 words
The test system of claim 8 wherein the alignment member comprises a beveled edge along a periphery the component.
Claim 13
Dependent Claim
25 words
The test system as claimed in claim 8 wherein the alignment member comprises a polymer layer on the interconnect comprising an opening with the surface.
Claim 14
Independent Claim
89 words
An apparatus for testing a semiconductor component having contact bumps comprising: an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, the contact members comprising indentations sized to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls at least partially covered with conductive layers and configured to guide the contact bumps into the indentations; and an alignment fixture comprising a polymer layer on the interconnect comprising an opening with a surface for aligning the component to the interconnect.
Claim 15
Independent Claim
89 words
An apparatus for testing a semiconductor component having contact bumps comprising: an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, the contact members comprising indentations sized to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls at least partially covered with conductive layers and configured to guide the contact bumps into the indentations; and an alignment fixture comprising a polymer layer on the interconnect comprising an opening with a surface for aligning the component to the interconnect.
Claim 16
Dependent Claim
15 words
The apparatus of claim 11 wherein the polymer layer comprises a patterned and developed resist.
Claim 17
Independent Claim
114 words
A method for fabricating a test system for semiconductor components comprising: providing a component comprising a plurality of external contact bumps and an alignment member; providing an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, each contact member comprising an indentation at least partially covered with a conductive layer and configured to retain and electrically contact a contact bump, the indentation comprising a sloped sidewall configured to guide the contact bump into the indentation; and forming an alignment fixture by depositing a polymer layer on the interconnect having a surface configured to engage the alignment member to align the contact bumps to the contact members.
Claim 18
Independent Claim
114 words
A method for fabricating a test system for semiconductor components comprising: providing a component comprising a plurality of external contact bumps and an alignment member; providing an interconnect comprising a plurality of contact members configured to make temporary electrical connections with the contact bumps, each contact member comprising an indentation at least partially covered with a conductive layer and configured to retain and electrically contact a contact bump, the indentation comprising a sloped sidewall configured to guide the contact bump into the indentation; and forming an alignment fixture by depositing a polymer layer on the interconnect having a surface configured to engage the alignment member to align the contact bumps to the contact members.
Claim 19
Dependent Claim
28 words
The method of claim 13 wherein the polymer layer comprises a layer of resist and the forming step comprises developing the resist with an opening comprising the surface.
Claim 20
Dependent Claim
24 words
The method of claim 13 wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
Claim 21
Independent Claim
112 words
A method for fabricating a test system for semiconductor components comprising: providing a component comprising a plurality of contact bumps and an alignment member; providing an interconnect comprising a plurality of contact members configured to make temporary electrical connection with the contact bumps, the contact members comprising indentations at least partially covered with conductive layers, the indentations sized to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; forming a resist layer on the interconnect; forming a surface on the resist layer configured to contact the alignment member to align the component with the interconnect; and curing the resist layer.
Claim 22
Independent Claim
112 words
A method for fabricating a test system for semiconductor components comprising: providing a component comprising a plurality of contact bumps and an alignment member; providing an interconnect comprising a plurality of contact members configured to make temporary electrical connection with the contact bumps, the contact members comprising indentations at least partially covered with conductive layers, the indentations sized to retain and electrically contact the contact bumps, the indentations comprising sloped sidewalls configured to guide the contact bumps into the indentations; forming a resist layer on the interconnect; forming a surface on the resist layer configured to contact the alignment member to align the component with the interconnect; and curing the resist layer.
Claim 23
Dependent Claim
16 words
The method of claim 16 wherein the surface comprises an opening in the layer of resist.
Claim 24
Dependent Claim
24 words
The method of claim 16 wherein the component comprises an element selected from the group consisting of chip scale packages and bumped semiconductor dice.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-24 | 2003-07-26 | 2004-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-24 | 2007-07-26 | 2008-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-24 | 2011-07-26 | 2012-01-25 | $7700.00 | Window Closed / Lapsed |