Integration of SAC and salicide processes by combining hard mask and poly definition

Claim 1

A method of combining hard mask and poly definition when forming contacts in an integrated circuit wafer that contains logic and memory areas, comprising the sequential steps of: providing a P type silicon wafer having a top surface; forming a layer of gate oxide on said surface; depositing on the wafer successive layers of first polysilicon and first silicon oxide; selectively removing said first silicon oxide layer from the memory area; depositing on the wafer successive layers of tungsten silicide, second silicon oxide, and silicon nitride; selectively removing the silicon nitride, second silicon oxide, tungsten silicide, and first oxide layers from the logic area; in the memory area only, patterning and etching the silicon nitride, second oxide, tungsten silicide, first polysilicon, and gate oxide layers to form memory gate pedestals having vertical walls; in the logic area only, patterning and etching the first polysilicon and gate oxide layers to form logic gate pedestals having vertical walls; forming N type source and drain regions adjacent to said vertical walls by means of ion implantation into said adjacent regions together with the formation of silicon nitride spacers on said vertical walls; selectively depositing a layer of resist protecting oxide on the memory area; depositing a layer of a silicide forming metal on the wafer; subjecting the wafer to a first rapid thermal anneal whereby the metal reacts to form a layer of silicide wherever it is in direct contact with silicon; removing all unreacted metal thereby forming self-aligned source, gate, and drain contacts in the logic area; subjecting the wafer to a second rapid thermal anneal; depositing a layer of inter poly oxide over the wafer sufficient to fully cover both the logic and the memory area; patterning and etching the inter poly oxide to form contact holes in the memory area; depositing a second polysilicon layer; and patterning and etching the second polysilicon layer to form connections in said contact holes.

Claim 2

A method of combining hard mask and poly definition when forming contacts in an integrated circuit wafer that contains logic and memory areas, comprising the sequential steps of: providing a P type silicon wafer having a top surface; forming a layer of gate oxide on said surface; depositing on the wafer successive layers of first polysilicon and first silicon oxide; selectively removing said first silicon oxide layer from the memory area; depositing on the wafer successive layers of tungsten silicide, second silicon oxide, and silicon nitride; selectively removing the silicon nitride, second silicon oxide, tungsten silicide, and first oxide layers from the logic area; in the memory area only, patterning and etching the silicon nitride, second oxide, tungsten silicide, first polysilicon, and gate oxide layers to form memory gate pedestals having vertical walls; in the logic area only, patterning and etching the first polysilicon and gate oxide layers to form logic gate pedestals having vertical walls; forming N type source and drain regions adjacent to said vertical walls by means of ion implantation into said adjacent regions together with the formation of silicon nitride spacers on said vertical walls; selectively depositing a layer of resist protecting oxide on the memory area; depositing a layer of a silicide forming metal on the wafer; subjecting the wafer to a first rapid thermal anneal whereby the metal reacts to form a layer of silicide wherever it is in direct contact with silicon; removing all unreacted metal thereby forming self-aligned source, gate, and drain contacts in the logic area; subjecting the wafer to a second rapid thermal anneal; depositing a layer of inter poly oxide over the wafer sufficient to fully cover both the logic and the memory area; patterning and etching the inter poly oxide to form contact holes in the memory area; depositing a second polysilicon layer; and patterning and etching the second polysilicon layer to form connections in said contact holes.