Manufacturing process for an integrated circuit comprising double gate components

Claim 1

A process for manufacturing integrated circuits comprising insulated gate MOS transistors and multi-gate devices on a semiconductor substrate, comprising the following steps: using insulating regions, separating the areas wherein the MOS transistors are to be formed from the areas wherein the multi-gate devices are to be formed; forming on the areas where the multi-gate devices are to be formed at least a first insulating layer and at least a first gate level; forming on the transistor areas and the multi-gate device areas a second insulating layer, a second gate level and a first photoresist mask layer; etching the first photoresist mask layer and the second gate level according to chosen patterns in the transistor areas and the areas of the multi-gate devices; coating the transistor areas with a second photoresist mask layer; selectively etching the second photoresist mask layer to form unmasked areas at the center of the places where the drains and sources of the transistors are to be formed; etching the unmasked areas of said second insulating layer in both the transistor areas and the multi-gate device areas and then the unmasked gate area of the multi-gate areas and the unmasked substrate areas of the transistor areas; removing the second photoresist mask layer; and carrying out an ionic implantation of the drains and sources in one single step.