EP0200364A1
Expired / Lapsed
EP
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Method of fabricating metal silicide gate electrodes and interconnections
Assignee: Advanced Micro Devices Inc
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Filing: 1986-03-27
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Granted: —
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Expires: 2006-03-27
Abstract
Abstract A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium (40) is overlayed on the die structure covering thereby the pre-patterned polysilicon gates (18, 36) and interconections. The die is then rapidly heated and baked to form a silicide layer (42) superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.
Inventors
- 👤 Jih-Chang Lien
- 👤 Hsingya Wang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 15:05
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/44; H10B69/00; H10P; H10P14/00; H10P14/40; H10P14/412; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
83 words
A method of forming metal silicide electrode and interconnection structures on an integrated circuit substrate having a patterned polysilicon layer superposing said substrate and circuit components, comprising the steps of: forming a thin film of metal on said substrate to form a stratified structure with said layer; heating said substrate; and baking said substrate such that said metal and said polysilicon react to form a substantially silicide layer, wherein said structure forms a pattern of metal silicide electrode and metal silicide interconnection structures.
Claim 2
Independent Claim
83 words
A method of forming metal silicide electrode and interconnection structures on an integrated circuit substrate having a patterned polysilicon layer superposing said substrate and circuit components, comprising the steps of: forming a thin film of metal on said substrate to form a stratified structure with said layer; heating said substrate; and baking said substrate such that said metal and said polysilicon react to form a substantially silicide layer, wherein said structure forms a pattern of metal silicide electrode and metal silicide interconnection structures.
Claim 3
Dependent Claim
33 words
The method according to Claim 1, wherein said step of forming a thin film of metal comprises: depositing a film of titanium having a thickness in the range of 500 to 1500 Angstroms.
Claim 4
Dependent Claim
31 words
The method according to Claim 1, wherein said step of heating said substrate comprises: rapidly raising the temperature of said substrate to within the range of 500 to 800 degrees centigrade.
Claim 5
Dependent Claim
31 words
The method according to Claim 3, wherein said step of baking said substrate comprises: maintaining said temperature for a period of time within the range of one second to 30 seconds.
Claim 6
Independent Claim
143 words
A method of forming metal silicide gate electrodes and metal silicide interconnections .on a semiconductor integrated circuit silicon substrate comprising the steps of: forming a first insulator layer over said silicon substrate; forming at least one polysilicon gate on said first layer; doping regions of said substrate on each side of said gate such that said dopant forms source, drain and channel regions with respect to said gate to create a transistor structure; thickening said first insulating layer not covered by said gate to a thickness so as to surround said gate; forming a layer of titanium on said gate and first insulator layer; heating said substrate; baking said substrate to allow said titanium and said polysilicon to react so as to form a homogeneous titanium silicide gate electrode superposing said channel region; and stripping said titanium layer from said first insulator layer.
Claim 7
Independent Claim
143 words
A method of forming metal silicide gate electrodes and metal silicide interconnections .on a semiconductor integrated circuit silicon substrate comprising the steps of: forming a first insulator layer over said silicon substrate; forming at least one polysilicon gate on said first layer; doping regions of said substrate on each side of said gate such that said dopant forms source, drain and channel regions with respect to said gate to create a transistor structure; thickening said first insulating layer not covered by said gate to a thickness so as to surround said gate; forming a layer of titanium on said gate and first insulator layer; heating said substrate; baking said substrate to allow said titanium and said polysilicon to react so as to form a homogeneous titanium silicide gate electrode superposing said channel region; and stripping said titanium layer from said first insulator layer.
Claim 8
Dependent Claim
17 words
The method as set forth in Claim 5, further comprising: forming a plurality of said transistor structure.
Claim 9
Dependent Claim
36 words
The method as set forth in Claim 6, further comprising: forming a pattern of polysilicon interconnections between said transistors prior to said step of thickening said insulator layer such that said layer also surrounds said interconnections.
Claim 10
Dependent Claim
33 words
The method according to Claim 7, wherein said step of forming a thin film of metal comprises: depositing a film of titanium having a thickness in the range of 500 to 1500 Angstroms.
Claim 11
Dependent Claim
31 words
The method according to Claim 8, wherein said step of heating said substrate comprises: rapidly raising the temperature of said substrate to within the range of 500 to 800 degrees centigrade.
Claim 12
Dependent Claim
31 words
The method according to Claim 9, wherein said step of baking said substrate comprises: maintaining said temperature for a period of time wihtin the range of one second to 30 seconds..
Claim 13
Dependent Claim
18 words
The method according to Claim 10, wherein said substrate has active integrated circuit components integral therewith, further comprising:
Claim 14
Dependent Claim
16 words
patterning said interconnections such that said transistors are connected to at least some of said components.
Claim 15
Dependent Claim
16 words
patterning said interconnections such that said transistors are connected to at least some of said components.
References Cited (Backward Citations)
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