← Back to Patent Explorer
EP0124960A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Semiconductor devices comprising silicides

Assignee: STC PLC
•
Filing: 1984-02-16
•
Granted: —
•
Expires: 2004-02-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallisation. After polysilicon metallisation the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24).

Inventors

  • 👤 Peter Denis Scovell
  • 👤 Paul John Rosser
  • 👤 Gary John Tomkins

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 04:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0212; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/01322; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 91 words
A method of manufacturing semiconductor devices characterised in that the steps of defining at least one polysilicon element (24) on an oxidised surface (23) of a silicon substrate (20), metallising (25) the at least one defined polysilicon element (24) including sidewalls thereof, and causing interdiffusion of the metal (25) and the polysilicon (24) whereby to form a metallic silicide layer (26) extending over the at least one defined polysilicon element (24) and up to the said oxidised surface (23) on which the at least one defined polysilicon element (24) is disposed.
Claim 2
Independent Claim 91 words
A method of manufacturing semiconductor devices characterised in that the steps of defining at least one polysilicon element (24) on an oxidised surface (23) of a silicon substrate (20), metallising (25) the at least one defined polysilicon element (24) including sidewalls thereof, and causing interdiffusion of the metal (25) and the polysilicon (24) whereby to form a metallic silicide layer (26) extending over the at least one defined polysilicon element (24) and up to the said oxidised surface (23) on which the at least one defined polysilicon element (24) is disposed.
Claim 3
Dependent Claim 24 words
A method as claimed in claim 1, characterised in that the at least one polysilicon element (24) comprises a polysilicon gate and/or an interconnection.
Claim 4
Dependent Claim 51 words
A method as claimed in claim 1 or claim 2, characterised in that those portions of the oxidised surface (23) of the silicon substrate surrounding the at least one polysilicon element (24) are metallised during the metallisation step, and wherein the metal is removed from said portions after the interdiffusion step.
Claim 5
Independent Claim 39 words
A method as claimed in any one of the preceding claims characterised in that the step of defining source and drain regions (21, 22) in the substrate (20) prior to definition of the at least one polysilicon element (24).
Claim 6
Independent Claim 18 words
A method as claimed in any one of the preceding claims characterised in that the metal is titanium.
Claim 7
Dependent Claim 21 words
A method as claimed in claim 5, characterised in that the interdiffusion is achieved by pulse annealing in an inert atmosphere.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag