US5858830A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making dual isolation regions for logic and embedded memory devices
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-06-12
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Granted: 1999-01-12
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Expires: 2017-06-12
Abstract
Abstract A method for forming thick field oxide regions, to be used for isolation in MOSFET memory regions, while also forming insulator filled, narrow trenches, to be used for isolation purposes in MOSFET logic regions, has been developed. The fabrication process features initially creating thick field oxide regions, in the MOSFET memory region, obtained via thermal oxidation procedures, followed by creation of a narrow trench opening, in the MOSFET logic region. An ozone aided, silicon oxide, CVD deposition, is used to fill the narrow trench openings, followed by a selective chemical mechanical polishing procedure, used to remove unwanted regions of silicon oxide layer, creating an insulator filled, narrow trench isolation, in the MOSFET logic region.
Inventors
- 👤 Chue-San Yoo
- 👤 Mong-Song Liang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 03:27
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10B; H10B99/00; H10B99/22; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
291 words
A method for forming a thick FOX isolation region, in an area of a semiconductor substrate to be used for a MOSFET memory region, while forming an insulator filled, trench isolation region, in an area of said semiconductor substrate to be used for a MOSFET logic region, comprising the steps of: forming a pad oxide layer on said semiconductor substrate; depositing a silicon nitride layer on said pad oxide layer; forming an opening in said silicon nitride layer, and in said pad oxide layer, exposing said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET memory region; thermally growing a thick FOX isolation region in said semiconductor substrate, exposed in said opening in said silicon nitride layer and in said pad oxide layer; forming a trench opening having exposed surfaces in said silicon nitride layer, in said pad oxide layer, and in said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET logic region; growing a thin silicon oxide layer on the exposed surfaces of said trench opening; depositing an insulator layer on the top surface of said silicon nitride layer, on the top surface of said thick FOX isolation regions, and completely filling said trench opening; removing said insulator layer from said top surface of said silicon nitride layer, and from said top surface of said thick FOX isolation region, and leaving said insulator layer in said trench opening, forming said insulator filled, trench isolation region, in an area of said semiconductor substrate, used for said MOSFET logic region; removing said silicon nitride layer, and said pad oxide layer; and forming polysilicon gate structures, and source and drain regions, in said MOSFET memory region, and in said MOSFET logic region.
Claim 2
Independent Claim
291 words
A method for forming a thick FOX isolation region, in an area of a semiconductor substrate to be used for a MOSFET memory region, while forming an insulator filled, trench isolation region, in an area of said semiconductor substrate to be used for a MOSFET logic region, comprising the steps of: forming a pad oxide layer on said semiconductor substrate; depositing a silicon nitride layer on said pad oxide layer; forming an opening in said silicon nitride layer, and in said pad oxide layer, exposing said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET memory region; thermally growing a thick FOX isolation region in said semiconductor substrate, exposed in said opening in said silicon nitride layer and in said pad oxide layer; forming a trench opening having exposed surfaces in said silicon nitride layer, in said pad oxide layer, and in said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET logic region; growing a thin silicon oxide layer on the exposed surfaces of said trench opening; depositing an insulator layer on the top surface of said silicon nitride layer, on the top surface of said thick FOX isolation regions, and completely filling said trench opening; removing said insulator layer from said top surface of said silicon nitride layer, and from said top surface of said thick FOX isolation region, and leaving said insulator layer in said trench opening, forming said insulator filled, trench isolation region, in an area of said semiconductor substrate, used for said MOSFET logic region; removing said silicon nitride layer, and said pad oxide layer; and forming polysilicon gate structures, and source and drain regions, in said MOSFET memory region, and in said MOSFET logic region.
Claim 3
Dependent Claim
35 words
The method of claim 1, wherein said silicon nitride layer is obtained via LPCVD or PECVD procedures at a temperature between about 300° to 500° C., to a thickness between about 1500 to 2000 Angstroms.
Claim 4
Dependent Claim
44 words
The method of claim 1, wherein said thick FOX isolation region is formed via thermal oxidation of said semiconductor substrate, in an oxygen - steam ambient, at a temperature between about 800° to 1200° C., to a thickness between about 3000 to 5000 Angstroms.
Claim 5
Dependent Claim
49 words
The method of claim 1, wherein said trench opening is formed via anisotropic RIE procedures, using CHF 3 as an etchant for said silicon nitride layer, and for said pad oxide layer, while Cl 2 is used as an etchant to form said trench opening in said semiconductor substrate.
Claim 6
Dependent Claim
31 words
The method of claim 1, wherein said trench opening has a diameter between about 0.10 to 1.0 uM, and a depth, in said semiconductor substrate, between about 3000 to 5000 Angstroms.
Claim 7
Dependent Claim
47 words
The method of claim 1, wherein said insulator layer, used to fill said trench opening, is silicon oxide, deposited using SACVD procedures, at a temperature between about 300° to 500° C., to a thickness between about 3000 to 5000 Angstroms, using ozone and TEOS as a source.
Claim 8
Dependent Claim
35 words
The method of claim 1, wherein said insulator layer is selectively removed from the top surface of said silicon nitride layer, and from the top surface of said thick FOX isolation regions, using CMP procedures.
Claim 9
Dependent Claim
27 words
The method of claim 1, wherein said silicon nitride layer is removed using a hot phosphoric acid solution, at a temperature between about 65° to 150° C.
References Cited (Backward Citations)
US4352236A
Cited
US4980311A
Cited
US5466623A
Cited
US5061654A
Cited
US4981812A
Cited
US5173436A
Cited
US5112772A
Cited
US5455438A
Cited
US5506160A
Cited
US5683921A
Cited
US5728620A
Cited
US5712205A
Cited
US5677232A
Cited
US5731221A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |