Process for fabricating a semiconductor read only memory

Claim 2

A process for fabricating a semiconductor read only memory, comprising the steps of: growing a gate insulating film on a semiconductor substrate; growing a first polycrystalline silicon layer and a silicon nitride film on said gate insulating film; providing element separating trenches each passing through said gate insulating film, said first polycrystalline silicon layer, and said silicon nitride film to reach said semiconductor substrate; growing oxidation films on an inner surface of said element separating trenches; growing a second polycrystalline silicon layer to be buried into said element separating trenches; growing a thermal oxidation film on said second polycrystalline silicon layer by use of a mask utilizing said silicon nitride film; providing a conductive layer on said first polycrystalline silicon layer and said thermal oxidation film after removing said silicon nitride film; providing plural gate electrodes by selective etching of said conductive layer and said first polycrystalline silicon layer; and providing source and drain regions by use of a mask utilizing said gate electrodes.

Claim 3

A process for fabricating a semiconductor read only memory, according to claim 1, wherein: said semiconductor substrate, includes: a semiconductor substrate doped with impurities by a high concentration; and an epitaxial layer grown on said doped semiconductor substrate; and said element separating trenches are provided by an entire thickness of said epitaxial layer.

Claim 4

A process for fabricating a semiconductor read only memory, comprising the steps of: providing a field oxidation film selectively on a semiconductor substrate; growing a gate oxidation film on said semiconductor substrate; growing a first polycrystalline silicon layer having a predetermined thickness on said field oxidation film; growing a mask oxidation film having a predetermined thickness on said first polycrystalline silicon layer; providing a silicon nitride film on said mask oxidation film; providing photoresists on said silicon nitride film; providing element separating trenches each reaching said semiconductor substrate with a predetermined depth by use of said photoresists; removing said photoresists out of an surface of said silicon nitride; growing trench oxidation films on an inner surface of said element separating trenches; removing said trench oxidation films on each bottom surface of said element separating trenches; providing a second polycrystalline silicon layer in said element separating trenches and on said silicon nitride film; etching said second polycrystalline silicon layer selectively by use of a mask of said silicon nitride film; growing insulating oxidation film each having a predetermined thickness on said second polycrystalline silicon layers selectively left in said etching; removing said silicon nitride film and said mask oxidation films over a surface of said semiconductor substrate; forming WSi layer over said surface of said semiconductor substrate to provide a gate electrode; providing an impurity diffusion layer in said semiconductor substrate by use of a mask of said gate electrode; forming a mask to provide a ROM code and removing said mask of said ROM code after said ROM code is provided; providing a first insulating film having a first contact over said semiconductor substrate; forming WSi wiring layer passing through said first contact to reach said impurity diffusion layer, thereby providing a source electrode; providing a second insulating film having a second contact over said semiconductor substrate; and forming aluminum wiring layer passing through said second contact to reach said impurity diffusion layer, thereby providing a drain electrode.

Claim 5

A process for fabricating a semiconductor read only memory, comprising the steps of: providing a field oxidation film selectively on a semiconductor substrate; growing a gate oxidation film on said semiconductor substrate; growing a first polycrystalline silicon layer having a predetermined thickness on said field oxidation film; growing a mask oxidation film having a predetermined thickness on said first polycrystalline silicon layer; providing a silicon nitride film on said mask oxidation film; providing photoresists on said silicon nitride film; providing element separating trenches each reaching said semiconductor substrate with a predetermined depth by use of said photoresists; removing said photoresists out of an surface of said silicon nitride; growing trench oxidation films on an inner surface of said element separating trenches; removing said trench oxidation films on each bottom surface of said element separating trenches; providing a second polycrystalline silicon layer in said element separating trenches and on said silicon nitride film; etching said second polycrystalline silicon layer selectively by use of a mask of said silicon nitride film; growing insulating oxidation film each having a predetermined thickness on said second polycrystalline silicon layers selectively left in said etching; removing said silicon nitride film and said mask oxidation films over a surface of said semiconductor substrate; forming WSi layer over said surface of said semiconductor substrate to provide a gate electrode; providing an impurity diffusion layer in said semiconductor substrate by use of a mask of said gate electrode; forming a mask to provide a ROM code and removing said mask of said ROM code after said ROM code is provided; providing a first insulating film having a first contact over said semiconductor substrate; forming WSi wiring layer passing through said first contact to reach said impurity diffusion layer, thereby providing a source electrode; providing a second insulating film having a second contact over said semiconductor substrate; and forming aluminum wiring layer passing through said second contact to reach said impurity diffusion layer, thereby providing a drain electrode.