Integration of sac and salicide processes on a chip having embedded memory

Claim 1

A method of forming contacts in an integrated circuit that contains logic and memory areas, comprising the sequential steps of: providing a P type silicon wafer; depositing on the wafer successive layers of gate oxide, first polysilicon, first silicon oxide, and silicon nitride; patterning and etching the silicon nitride to form a hard mask; forming gate pedestals having vertical sides by removing the silicon oxide and first polysilicon layers wherever they are not protected by said hard mask; coating the wafer with a BPR layer to a thickness sufficient to lower the gates, including the layer of silicon nitride; coating the BPR layer with photoresist that is patterned to cover only the memory area; etching the BPR layer, thereby uncovering the silicon nitride layer in the logic area; removing the uncovered silicon nitride, the photoresist and the BPR layers; forming N type source and drain regions adjacent to said vertical sides by means of ion implantation into said adjacent regions together with the formation of spacers on said vertical sides; depositing a layer of resist protecting oxide on the wafer; selectively removing the resist protecting oxide from the logic area; depositing a layer of a silicide forming metal on the wafer; subjecting the wafer to a first rapid thermal anneal whereby the metal reacts to form a layer of silicide wherever it is in direct contact with silicon; removing all unreacted metal thereby forming self-aligned source, gate, and drain contacts in the logic area; subjecting the wafer to a second rapid thermal anneal; depositing a layer of inter poly oxide over the wafer sufficient to fully cover both the logic and the memory area; patterning and etching the inter poly oxide to form contact holes in the memory area; depositing a second polysilicon layer; and patterning and etching the second polysilicon layer to form connections to said contact holes.

Claim 2

A method of forming contacts in an integrated circuit that contains logic and memory areas, comprising the sequential steps of: providing a P type silicon wafer; depositing on the wafer successive layers of gate oxide, first polysilicon, first silicon oxide, and silicon nitride; patterning and etching the silicon nitride to form a hard mask; forming gate pedestals having vertical sides by removing the silicon oxide and first polysilicon layers wherever they are not protected by said hard mask; coating the wafer with a BPR layer to a thickness sufficient to lower the gates, including the layer of silicon nitride; coating the BPR layer with photoresist that is patterned to cover only the memory area; etching the BPR layer, thereby uncovering the silicon nitride layer in the logic area; removing the uncovered silicon nitride, the photoresist and the BPR layers; forming N type source and drain regions adjacent to said vertical sides by means of ion implantation into said adjacent regions together with the formation of spacers on said vertical sides; depositing a layer of resist protecting oxide on the wafer; selectively removing the resist protecting oxide from the logic area; depositing a layer of a silicide forming metal on the wafer; subjecting the wafer to a first rapid thermal anneal whereby the metal reacts to form a layer of silicide wherever it is in direct contact with silicon; removing all unreacted metal thereby forming self-aligned source, gate, and drain contacts in the logic area; subjecting the wafer to a second rapid thermal anneal; depositing a layer of inter poly oxide over the wafer sufficient to fully cover both the logic and the memory area; patterning and etching the inter poly oxide to form contact holes in the memory area; depositing a second polysilicon layer; and patterning and etching the second polysilicon layer to form connections to said contact holes.