Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic

Claim 1

A method of forming an SRAM (Static Random Access Memory), a mixed-mode capacitor, and logic on a single semiconductor substrate, in a first memory region, a capacitor region, and a logic region, respectively, comprising the steps of: providing a semiconductor substrate; forming field isolation regions in said semiconductor substrate; forming a gate oxide over said substrate between said field isolation regions; depositing a first polysilicon layer over said gate oxide; patterning said first polysilicon layer, comprising: forming gates over a portion of said gate oxide; forming polysilicon interconnects over a portion of said field isolation regions, only in said first memory region; and forming a bottom capacitor plate over a field oxide region in said capacitor region; forming lightly doped drain (LDD) active regions in said substrate, adjacent to each said gate; forming insulating spacers on the sidewalls of said gates, polysilicon interconnects and bottom capacitor plate; completing formation of said active regions by a heavy ion implant; removing said insulating spacers from the sidewalls of said polysilicon interconnects; forming a layer of titanium silicide over said gates, polysilicon interconnects, bottom capacitor plate and active regions, whereby said titanium silicide electrically connects said polysilicon interconnects and said active regions in said first memory region; forming an interpoly oxide over said semiconductor substrate; forming an opening in said interpoly oxide over said polysilicon interconnect; depositing a second layer of polysilicon over said substrate; and patterning said second layer of polysilicon to form a to form a top capacitor plate over said bottom capacitor plate, and to form a load resistor for said SRAM.

Claim 2

A method of forming an SRAM (Static Random Access Memory), a mixed-mode capacitor, and logic on a single semiconductor substrate, in a first memory region, a capacitor region, and a logic region, respectively, comprising the steps of: providing a semiconductor substrate; forming field isolation regions in said semiconductor substrate; forming a gate oxide over said substrate between said field isolation regions; depositing a first polysilicon layer over said gate oxide; patterning said first polysilicon layer, comprising: forming gates over a portion of said gate oxide; forming polysilicon interconnects over a portion of said field isolation regions, only in said first memory region; and forming a bottom capacitor plate over a field oxide region in said capacitor region; forming lightly doped drain (LDD) active regions in said substrate, adjacent to each said gate; forming insulating spacers on the sidewalls of said gates, polysilicon interconnects and bottom capacitor plate; completing formation of said active regions by a heavy ion implant; removing said insulating spacers from the sidewalls of said polysilicon interconnects; forming a layer of titanium silicide over said gates, polysilicon interconnects, bottom capacitor plate and active regions, whereby said titanium silicide electrically connects said polysilicon interconnects and said active regions in said first memory region; forming an interpoly oxide over said semiconductor substrate; forming an opening in said interpoly oxide over said polysilicon interconnect; depositing a second layer of polysilicon over said substrate; and patterning said second layer of polysilicon to form a to form a top capacitor plate over said bottom capacitor plate, and to form a load resistor for said SRAM.

Claim 11

A method of forming a local interconnect in an SRAM simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, wherein a mixed mode capacitor is also formed, comprising the steps of: providing a semiconductor substrate having MOS (Metal Oxide Semiconductor) transistors formed therein, separated by field isolation regions, each said transistor comprising a gate overlying a gate oxide and having source and drain regions in said substrate, with spacers on the sidewalls of said gates, wherein some of said field oxide regions in said SRAM have polysilicon interconnects, with sidewall spacers, thereover, and wherein a bottom capacitor plate is formed over the field isolation region for said mixed mode capacitor; removing said sidewall spacers from said polysilicon interconnects; forming a first interpoly oxide over said bottom capacitor plate; depositing a layer of titanium over said semiconductor substrate; and forming said salicide over said gates, said source and drain regions, and said polysilicon interconnects, and whereby said local interconnect is formed connecting said polysilicon interconnects to one of said source regions.

Claim 12

A method of forming a local interconnect in an SRAM simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, wherein a mixed mode capacitor is also formed, comprising the steps of: providing a semiconductor substrate having MOS (Metal Oxide Semiconductor) transistors formed therein, separated by field isolation regions, each said transistor comprising a gate overlying a gate oxide and having source and drain regions in said substrate, with spacers on the sidewalls of said gates, wherein some of said field oxide regions in said SRAM have polysilicon interconnects, with sidewall spacers, thereover, and wherein a bottom capacitor plate is formed over the field isolation region for said mixed mode capacitor; removing said sidewall spacers from said polysilicon interconnects; forming a first interpoly oxide over said bottom capacitor plate; depositing a layer of titanium over said semiconductor substrate; and forming said salicide over said gates, said source and drain regions, and said polysilicon interconnects, and whereby said local interconnect is formed connecting said polysilicon interconnects to one of said source regions.