US5066602A
Expired / Lapsed
US
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Method of making semiconductor ic including polar transistors
Assignee: Panasonic Holdings Corp
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Filing: 1989-01-10
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Granted: 1991-11-19
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Expires: 2009-01-10
Abstract
Abstract In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p - -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p - -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p - -regions (40) and (49) are formed simultaneously with the p - -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p - -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.
Inventors
- 👤 Toyoki Takemoto
- 👤 Tadao Komeda
- 👤 Haruyasu Yamada
- 👤 Tsutomu Fujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/658; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/67; H10D84/673; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01; H10D84/83138; H10D84/8314; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/151
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
197 words
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second, third and fourth regions of n-type; forming fifth and sixth regions of low p-type concentration in said first and second regions from upper surfaces of said first and second regions respectively; forming seventh and eight regions of p-type in said third region from an upper surface of said third region simultaneously to said forming fifth and sixth regions step; forming a ninth region of an n-type in said fifth region from a upper surface of said fifth region; forming tenth, eleventh, twelfth, thirteenth and fourteenth regions of p-type in said ninth, sixth, seventh, eight and fourth regions from upper surfaces of said ninth, sixth, seventh, eighth and fourth regions respectively; and forming fifteenth, sixteenth and seventeenth regions of n-type in said ninth, eighth and fourteenth regions from upper surfaces of said ninth, eighth and fourteenth regions respectively, whereby a pnp type vertical bipolar transistor, resistance device, logic circuit and an npn type vertical bipolar transistor are formed in said first, second, third and fourth regions respectively.
Claim 2
Independent Claim
197 words
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second, third and fourth regions of n-type; forming fifth and sixth regions of low p-type concentration in said first and second regions from upper surfaces of said first and second regions respectively; forming seventh and eight regions of p-type in said third region from an upper surface of said third region simultaneously to said forming fifth and sixth regions step; forming a ninth region of an n-type in said fifth region from a upper surface of said fifth region; forming tenth, eleventh, twelfth, thirteenth and fourteenth regions of p-type in said ninth, sixth, seventh, eight and fourth regions from upper surfaces of said ninth, sixth, seventh, eighth and fourth regions respectively; and forming fifteenth, sixteenth and seventeenth regions of n-type in said ninth, eighth and fourteenth regions from upper surfaces of said ninth, eighth and fourteenth regions respectively, whereby a pnp type vertical bipolar transistor, resistance device, logic circuit and an npn type vertical bipolar transistor are formed in said first, second, third and fourth regions respectively.
Claim 3
Dependent Claim
22 words
A method as in claim 1, wherein said twelfth and thirteenth regions are formed in a projected manner in said third region.
Claim 4
Independent Claim
195 words
A method of fabricating a semiconductor circuit, comprising the steps of: (a) forming an n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; (b) simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; (c) forming a sixth region of an n-type in said fifth region from an upper surface of said fifth region; (d) simultaneously forming seventh and eighth regions of p-type in said sixth and third regions respectively from upper surfaces of said sixth and third regions; (e) simultaneously forming ninth, tenth and eleventh regions of n-type in said fourth and eighth regions from upper surfaces of said fourth and eighth regions, respectively, such that said fifth, sixth and seventh regions form a pnp type vertical bipolar transistor and said third, eighth, and eleventh regions form a vertical npn transistor; and (f) selectively forming an insulation layer on said fourth region, and forming a polycrystalline silicon gate electrode on said insulation layer such that said fourth, ninth and tenth regions form an n-channel MOS transistor.
Claim 5
Independent Claim
195 words
A method of fabricating a semiconductor circuit, comprising the steps of: (a) forming an n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; (b) simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; (c) forming a sixth region of an n-type in said fifth region from an upper surface of said fifth region; (d) simultaneously forming seventh and eighth regions of p-type in said sixth and third regions respectively from upper surfaces of said sixth and third regions; (e) simultaneously forming ninth, tenth and eleventh regions of n-type in said fourth and eighth regions from upper surfaces of said fourth and eighth regions, respectively, such that said fifth, sixth and seventh regions form a pnp type vertical bipolar transistor and said third, eighth, and eleventh regions form a vertical npn transistor; and (f) selectively forming an insulation layer on said fourth region, and forming a polycrystalline silicon gate electrode on said insulation layer such that said fourth, ninth and tenth regions form an n-channel MOS transistor.
Claim 6
Dependent Claim
104 words
A method in accordance with claim 3 comprising the further steps of: simultaneously to forming said sixth region, forming a twelfth region of an n-type in said first region from an upper surface of said first region; simultaneously to forming said seventh and eighth regions, forming thirteenth and fourteenth regions of p-type in said twelfth region; simultaneously to forming said insulation layer, selectively forming another insulation layer on said twelfth region; and simultaneously to forming said polycrystalline silicon gate electrode, forming a polycrystalline silicon gate electrode on said another insulation layer, such that said twelfth, thirteenth and fourteenth regions form a p-channel MOS transistor.
Claim 7
Independent Claim
186 words
A method of fabricating a semiconductor circuit, comprising the steps of: (a) forming an n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; (b) forming a fourth region of low p-type concentration in said second region as an upper surface of said second region; (c) forming a fifth region of n-type in said fourth region from an upper surface of said fourth region; (d) simultaneously forming sixth, seventh, eighth and ninth regions of p-type in said first, fifth and third regions respectively from upper surfaces of said first, fifth and third regions; (e) forming a tenth region of n-type in said ninth region from an upper surface of said ninth region, whereby said fourth, fifth and eighth regions form a pnp type vertical bipolar transistor, and said third, ninth and tenth regions form an npn type vertical bipolar transistor; and (f) selectively forming an insulation layer on said first region and forming a polycrystalline silicon gate electrode on said insulation layer whereby said first, sixth and seventh regions form a p-channel MOS transistor.
Claim 8
Independent Claim
186 words
A method of fabricating a semiconductor circuit, comprising the steps of: (a) forming an n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; (b) forming a fourth region of low p-type concentration in said second region as an upper surface of said second region; (c) forming a fifth region of n-type in said fourth region from an upper surface of said fourth region; (d) simultaneously forming sixth, seventh, eighth and ninth regions of p-type in said first, fifth and third regions respectively from upper surfaces of said first, fifth and third regions; (e) forming a tenth region of n-type in said ninth region from an upper surface of said ninth region, whereby said fourth, fifth and eighth regions form a pnp type vertical bipolar transistor, and said third, ninth and tenth regions form an npn type vertical bipolar transistor; and (f) selectively forming an insulation layer on said first region and forming a polycrystalline silicon gate electrode on said insulation layer whereby said first, sixth and seventh regions form a p-channel MOS transistor.
Claim 9
Dependent Claim
113 words
A method in accordance with claim 5 comprising the further steps of: simultaneously to forming said fifth region, forming an eleventh region of an n-type in said first region from an upper surface of said first region; simultaneously to forming said sixth, seventh, eighth and ninth regions, forming twelfth and thirteenth regions of p-type in said eleventh region from an upper surface of said eleventh region; simultaneously to forming said insulation layer, selectively forming another insulation layer on said twelfth region; and simultaneously to forming said polycrystalline silicon gate electrode, forming a polycrystalline silicon gate electrode on said another insulation layer, whereby said eleventh, twelfth and thirteenth regions form a p-channel MOS transistor.
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