US4546539A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I2 L Structure and fabrication process compatible with high voltage bipolar transistors
Assignee: Intersil Corp
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Filing: 1982-12-08
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Granted: 1985-10-15
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Expires: 2002-12-08
Abstract
Abstract An integrated circuit wherein the base and surface collector regions of the I 2 L vertical transistor are formed by the same steps used to form the collector and base, respectively, of complementary bipolar transistors. Thus, a high voltage bipolar transistor of the same type as the vertical I 2 L transistor may be formed using separate process steps, thereby optimizing the design of both devices.
Inventors
- 👤 James D. Beasom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:39
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/085; Y10S148/087; Y10S148/151
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
176 words
A method of fabricating vertical bipolar transistors and an integrated injection logic device simultaneously comprising: introducing and diffusing impurities of a first conductivity type into a first and second isolated substrate region of a second conductivity type opposite said first conductivity type to form a collector region of said vertical bipolar transistor in said first substrate region and a base region of said logic in said second substrate region; introducing impurities of said second conductivity type into said vertical bipolar collector region to form a base region, and into said logic base region to form a collector region; introducing impurities of said first conductivity type into said second substrate region to form an injector region; introducing impurities of said first conductivity type into said vertical bipolar base region to form an emitter region; introducing impurities of said second conductivity type into said vertical bipolar base region to form a base contact region, into said logic collector region to form a collector contact region, and into said second substrate region to form a logic emitter contact region.
Claim 2
Independent Claim
176 words
A method of fabricating vertical bipolar transistors and an integrated injection logic device simultaneously comprising: introducing and diffusing impurities of a first conductivity type into a first and second isolated substrate region of a second conductivity type opposite said first conductivity type to form a collector region of said vertical bipolar transistor in said first substrate region and a base region of said logic in said second substrate region; introducing impurities of said second conductivity type into said vertical bipolar collector region to form a base region, and into said logic base region to form a collector region; introducing impurities of said first conductivity type into said second substrate region to form an injector region; introducing impurities of said first conductivity type into said vertical bipolar base region to form an emitter region; introducing impurities of said second conductivity type into said vertical bipolar base region to form a base contact region, into said logic collector region to form a collector contact region, and into said second substrate region to form a logic emitter contact region.
Claim 3
Dependent Claim
54 words
The method of claim 1 including introducing impurities of said second conductivity type in said second substrate region to form a shield region for said logic simultaneously with the formulation of said logic collector region and wherein said injector region is formed in said shield region to have depth less than said shield region.
Claim 4
Dependent Claim
38 words
The method of claim 2 wherein said shield region is formed to extend into said logic base region and said injector region is formed in a portion of said shield region which extends into said logic base region.
Claim 5
Dependent Claim
26 words
The method of claim 1 when introducing said first conductivity type impurities to form said injector region and said vertical bipolar emitter region are performed simultaneously.
Claim 6
Dependent Claim
23 words
The method of claim 1 including introducing first conductivity type impurities into said logic base region to form a logic base contact region.
Claim 7
Dependent Claim
34 words
The method of claim 1 wherein said logic base region is formed to extend from the surface of said substrate to a buried layer of said second conductivity type in said second substrate region.
Claim 8
Dependent Claim
69 words
The method of claim 6 wherein said introduction and diffusion of first conductiveity type impurities is introduced through the back surface of said substrate before the formation of said buried layer followed by forming said buried layer by introducing impurities into said back surface, dividing said substrate into wells and applying a dielectric layer on said back surface, and continuing said process by introducing impurities through said top surface.
Claim 9
Dependent Claim
31 words
The method of claim 1 wherein said first conductivity impurities are diffused to form said vertical bipolar collector region and said logic base region to a depth of at least 8microns.
Claim 10
Dependent Claim
33 words
The method of claim 8 wherein said second conductivity type impurities are diffused to form said vertical bipolar base region and said logic collector region to a depth of at least 2.5 microns.
Claim 11
Dependent Claim
82 words
The method according to claim 1 including: introducing first conductivity type impurities into a third isolated substrate region to form a base region of a second vertical bipolar transistor after the formation of said logic base region; and introducing second conductivity type impurities into said third substrate region and said second vertical bipolar base region to form a collector contact region and an emitter region respectively of said second vertical bipolar transistor simultaneously with the formation of said logic collector contact region.
Claim 12
Dependent Claim
80 words
The method according to claim 1 including: introducing first conductivity type impurities into a third isolated substrate region to form a base region of a second bipolar transistor simultaneously with the formulation of said logic injector region; and introducing second conductivity type impurities into said third substrate region and said second bipolar base region to form a collector contact region and an emitter region respectively of said second bipolar transistor simultaneously with the formulation of said logic collector contact region.
Claim 13
Independent Claim
211 words
A method of fabricating complementary vertical bipolar transistors and an integrated injection logic device simultaneously comprising: introducing and diffusing impurities of a first conductivity type into a first and second isolated substrate region of a second conductivity type opposite said first conductivity type to form a collector region of a first vertical bipolar transistor in said first substrate region and a base region of an integrated injection logic device in said second substrate region; introducing and diffusing impurities of said second conductivity type into said second isolated substrate region to form a buried layer; introducing impuities of said first conductivity type into a third isolated substrate region to form a base region of a second vertical bipolar transistor complementary to said first vertical bipolar transistor; introducing impurities of said second conductivity type into said logic base region to form a collector region and into said second vertical bipolar base region to form an emitter region; introducing impuities of said second conductivity type into said first vertical bipolar collector region to form a base region; introducing impurities of said first conductivity type into said second substrate region to form an injector region; and introducing impurities of said first conductivity type into said first vertical bipolar base region to form an emitter region.
Claim 14
Independent Claim
211 words
A method of fabricating complementary vertical bipolar transistors and an integrated injection logic device simultaneously comprising: introducing and diffusing impurities of a first conductivity type into a first and second isolated substrate region of a second conductivity type opposite said first conductivity type to form a collector region of a first vertical bipolar transistor in said first substrate region and a base region of an integrated injection logic device in said second substrate region; introducing and diffusing impurities of said second conductivity type into said second isolated substrate region to form a buried layer; introducing impuities of said first conductivity type into a third isolated substrate region to form a base region of a second vertical bipolar transistor complementary to said first vertical bipolar transistor; introducing impurities of said second conductivity type into said logic base region to form a collector region and into said second vertical bipolar base region to form an emitter region; introducing impuities of said second conductivity type into said first vertical bipolar collector region to form a base region; introducing impurities of said first conductivity type into said second substrate region to form an injector region; and introducing impurities of said first conductivity type into said first vertical bipolar base region to form an emitter region.
Claim 15
Dependent Claim
71 words
The method of claim 12 wherein said introduction and diffusion of first conductivity type impurities is introduced through the bace surface of said substrate before the formation of said buried layer followed by forming said buried layer by introducing impurities into said back surface, dividing said said substrate into wells and applying a dielectric layer on the sand back surface, and continuing said process by introducing impurities through said top surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-14 | 1989-04-15 | 1989-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-14 | 1993-04-15 | 1993-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-14 | 1997-04-15 | 1997-10-15 | $7700.00 | Window Closed / Lapsed |